公开(公告)号：US07834657B1

公开(公告)日：2010-11-16

申请号：US12685680

申请日：2010-01-12

申请人： Sunny Arora ,  Mukesh Bansal ,  Dipesh K. Gupta ,  Ankesh Jain ,  Gaurav Jain ,  Ritika Singh

发明人： Sunny Arora ,  Mukesh Bansal ,  Dipesh K. Gupta ,  Ankesh Jain ,  Gaurav Jain ,  Ritika Singh

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00384 ,  H03K17/302 ,  H03K2217/0018

摘要： An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output. The inverter circuit at least partially compensates for variations in a threshold voltage associated with switching of transistors that form the inverter module.

摘要翻译： 逆变器电路具有数字信号幅度转换器，其具有耦合到反相器电路输入节点的输入端和幅度转换器输出端。 正阈值电压补偿发生器具有耦合到幅度转换器输出的正阈值电压补偿发生器输入。 负阈值电压补偿发生器具有耦合到逆变器电路输入节点的负阈值电压补偿发生器输入和负阈值电压补偿发生器输出。 复用器具有耦合到正阈值电压补偿发生器输出的第一输入，耦合到负阈值电压补偿发生器输出的第二输入和多路复用器输出。 逆变器模块具有提供逆变器电路输出节点的输出，并且反相器模块输入耦合到多路复用器输出。 逆变器电路至少部分地补偿与形成逆变器模块的晶体管的切换相关的阈值电压的变化。

公开(公告)号：US08093929B2

公开(公告)日：2012-01-10

申请号：US12715396

申请日：2010-03-02

申请人： Ankesh Jain ,  Deependra Jain ,  Krishna Thakur

发明人： Ankesh Jain ,  Deependra Jain ,  Krishna Thakur

IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC分类号： H03K21/00

摘要： A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output.

摘要翻译： 可编程数字时钟信号分频器模块具有模块时钟输入，模块时钟输出，缩放因子输入，两个编程输入和三次输入。 具有主分频器模块输出和时钟输入的主分频器模块耦合到模块时钟输入。 次分频器模块包括多路复用器和由两个锁存器除以锁存时钟输入，耦合到主分频器模块输出。 在操作中，应用于缩放因子输入和编程输入的逻辑值导致主分配器模块将主数字时钟信号的第一序列周期处理为第一基本时钟信号并且处理后续的第二次循环序列 第二基本时钟信号。 第一基本时钟信号和第二基本时钟信号向次级分频器模块提供时钟脉冲序列。 时钟脉冲序列的边沿触发了两个锁存器的分频，这导致锁存输出时钟信号在分频输出端有两个锁存器，占空比为50％。 第三输入的逻辑值选择时钟脉冲序列或锁存器输出时钟信号，作为模块时钟输出端的模块时钟输出信号。

公开(公告)号：US20110215842A1

公开(公告)日：2011-09-08

申请号：US12715396

申请日：2010-03-02

申请人： Ankesh Jain ,  Deependra K. Jain ,  Krishna Thakur

发明人： Ankesh Jain ,  Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03K21/00

CPC分类号： H03K21/00

摘要： A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output.

摘要翻译： 可编程数字时钟信号分频器模块具有模块时钟输入，模块时钟输出，缩放因子输入，两个编程输入和三次输入。 具有主分频器模块输出和时钟输入的主分频器模块耦合到模块时钟输入。 次分频器模块包括多路复用器和由两个锁存器除以锁存时钟输入，耦合到主分频器模块输出。 在操作中，应用于缩放因子输入和编程输入的逻辑值导致主分配器模块将主数字时钟信号的第一序列周期处理为第一基本时钟信号并且处理后续的第二次循环序列 第二基本时钟信号。 第一基本时钟信号和第二基本时钟信号向次级分频器模块提供时钟脉冲序列。 时钟脉冲序列的边沿触发了两个锁存器的分频，这导致锁存输出时钟信号在分频输出端有两个锁存器，占空比为50％。 第三输入的逻辑值选择时钟脉冲序列或锁存器输出时钟信号，作为模块时钟输出端的模块时钟输出信号。