公开(公告)号：US08093929B2

公开(公告)日：2012-01-10

申请号：US12715396

申请日：2010-03-02

申请人： Ankesh Jain ,  Deependra Jain ,  Krishna Thakur

发明人： Ankesh Jain ,  Deependra Jain ,  Krishna Thakur

IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC分类号： H03K21/00

摘要： A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output.

摘要翻译： 可编程数字时钟信号分频器模块具有模块时钟输入，模块时钟输出，缩放因子输入，两个编程输入和三次输入。 具有主分频器模块输出和时钟输入的主分频器模块耦合到模块时钟输入。 次分频器模块包括多路复用器和由两个锁存器除以锁存时钟输入，耦合到主分频器模块输出。 在操作中，应用于缩放因子输入和编程输入的逻辑值导致主分配器模块将主数字时钟信号的第一序列周期处理为第一基本时钟信号并且处理后续的第二次循环序列 第二基本时钟信号。 第一基本时钟信号和第二基本时钟信号向次级分频器模块提供时钟脉冲序列。 时钟脉冲序列的边沿触发了两个锁存器的分频，这导致锁存输出时钟信号在分频输出端有两个锁存器，占空比为50％。 第三输入的逻辑值选择时钟脉冲序列或锁存器输出时钟信号，作为模块时钟输出端的模块时钟输出信号。

公开(公告)号：US20110215842A1

公开(公告)日：2011-09-08

申请号：US12715396

申请日：2010-03-02

申请人： Ankesh Jain ,  Deependra K. Jain ,  Krishna Thakur

发明人： Ankesh Jain ,  Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03K21/00

CPC分类号： H03K21/00

摘要： A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output.

摘要翻译： 可编程数字时钟信号分频器模块具有模块时钟输入，模块时钟输出，缩放因子输入，两个编程输入和三次输入。 具有主分频器模块输出和时钟输入的主分频器模块耦合到模块时钟输入。 次分频器模块包括多路复用器和由两个锁存器除以锁存时钟输入，耦合到主分频器模块输出。 在操作中，应用于缩放因子输入和编程输入的逻辑值导致主分配器模块将主数字时钟信号的第一序列周期处理为第一基本时钟信号并且处理后续的第二次循环序列 第二基本时钟信号。 第一基本时钟信号和第二基本时钟信号向次级分频器模块提供时钟脉冲序列。 时钟脉冲序列的边沿触发了两个锁存器的分频，这导致锁存输出时钟信号在分频输出端有两个锁存器，占空比为50％。 第三输入的逻辑值选择时钟脉冲序列或锁存器输出时钟信号，作为模块时钟输出端的模块时钟输出信号。

公开(公告)号：US09331698B2

公开(公告)日：2016-05-03

申请号：US14146721

申请日：2014-01-02

申请人： Deependra K. Jain ,  Krishna Thakur

发明人： Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03L7/06 ,  H03K19/0175 ,  H03L7/085 ,  H03K5/156 ,  H03L7/099

CPC分类号： H03K19/017509 ,  H03K5/1565 ,  H03L7/085 ,  H03L7/0995

摘要： A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.

摘要翻译： 用于跨越多个电路域的信号的电平移位电压的电平移位器电路包括输入级和驱动级。 输入级接收由环形振荡器产生的振荡信号，并产生反相振荡信号。 差分振荡信号被提供给驱动级，该电平将振荡信号的电压电平移动到环形振荡器的电源电压的电平。

公开(公告)号：US20150188543A1

公开(公告)日：2015-07-02

申请号：US14146721

申请日：2014-01-02

申请人： Deependra K. Jain ,  Krishna Thakur

发明人： Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03K19/0175 ,  H03K5/156 ,  H03L7/099 ,  H03L7/085

CPC分类号： H03K19/017509 ,  H03K5/1565 ,  H03L7/085 ,  H03L7/0995

摘要： A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.

摘要翻译： 用于跨越多个电路域的信号的电平移位电压的电平移位器电路包括输入级和驱动级。 输入级接收由环形振荡器产生的振荡信号，并产生反相振荡信号。 差分振荡信号被提供给驱动级，该电平将振荡信号的电压电平移动到环形振荡器的电源电压的电平。

公开(公告)号：US08248130B2

公开(公告)日：2012-08-21

申请号：US12786496

申请日：2010-05-25

申请人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinish Chandra Tripathi ,  Sanjay Kumar Wadhwa

发明人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinish Chandra Tripathi ,  Sanjay Kumar Wadhwa

IPC分类号： H03K3/17 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

摘要翻译： 用于校正由时钟发生器产生的时钟信号的占空比的占空比校正电路包括互补缓冲链，电平移位器电路和自偏置电路。 具有失真占空比的时钟信号及其补码提供给电平移位器电路。 电平移位器电路减小时钟信号和补码的电压幅值，并产生电平移位信号。 电平移位信号被提供给差分放大器，该差分放大器产生指示占空比中的失真幅度的控制信号。 控制信号用于校正时钟信号的占空比。 自偏置电路用于偏置差分放大器。

公开(公告)号：US08063678B2

公开(公告)日：2011-11-22

申请号：US13109013

申请日：2011-05-17

申请人： Sanjay K. Wadhwa ,  Krishna Thakur

发明人： Sanjay K. Wadhwa ,  Krishna Thakur

IPC分类号： H03L7/06

CPC分类号： H03L7/0896

摘要： A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal (64), and a replica bias circuit. The replica bias circuit has a first reference current source transistor, a second reference current source transistor and a reference node corresponding to the output terminal of the charge pump core circuit. The reference node is connected to gates of the second current source transistor and the second reference current source transistor. A first input of a regulator circuit is connected to the output terminal of the charge pump core circuit. A second input of the regulator circuit is connected to the reference node of the replica bias circuit. An output of the regulator circuit (54) is connected to gates of the first current source transistor and the first reference current source transistor.

摘要翻译： 电荷泵包括具有第一电流源晶体管，第二电流源晶体管和输出端子（64）的电荷泵芯电路和复制偏置电路。 复制偏置电路具有第一参考电流源晶体管，第二参考电流源晶体管和对应于电荷泵芯电路的输出端的参考节点。 参考节点连接到第二电流源晶体管和第二参考电流源晶体管的栅极。 调节器电路的第一输入端连接到电荷泵芯电路的输出端。 调节器电路的第二输入连接到复制偏置电路的参考节点。 调节器电路（54）的输出端连接到第一电流源晶体管和第一参考电流源晶体管的栅极。

公开(公告)号：US07965117B2

公开(公告)日：2011-06-21

申请号：US12436153

申请日：2009-05-06

申请人： Sanjay K. Wadhwa ,  Krishna Thakur

发明人： Sanjay K. Wadhwa ,  Krishna Thakur

IPC分类号： H03L7/06

CPC分类号： H03L7/0896

摘要： A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal (64), and a replica bias circuit. The replica bias circuit has a first reference current source transistor, a second reference current source transistor and a reference node corresponding to the output terminal of the charge pump core circuit. The reference node is connected to gates of the second current source transistor and the second reference current source transistor. A first input of a regulator circuit is connected to the output terminal of the charge pump core circuit. A second input of the regulator circuit is connected to the reference node of the replica bias circuit. An output of the regulator circuit (54) is connected to gates of the first current source transistor and the first reference current source transistor.

公开(公告)号：US20100271138A1

公开(公告)日：2010-10-28

申请号：US12428490

申请日：2009-04-23

申请人： Krishna Thakur ,  Deependra K. Jain ,  Vinod Jain

发明人： Krishna Thakur ,  Deependra K. Jain ,  Vinod Jain

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L7/0898 ,  H03L7/10 ,  H03L2207/06

摘要： A phase-locked loop (PLL) system generates an oscillator signal based on an input reference signal. A calibration circuit generates a calibration current, and a voltage-to-current converter converts a control voltage into a first current. A current-controlled oscillator generates the oscillator signal based on the first current and the calibration current. A charge pump circuit, which is connected to a phase detector, the voltage-to-current converter, and the calibration circuit, generates a charge pump current based on the first current and the calibration current. The charge pump current is used to generate the control voltage based on an error signal.

摘要翻译： 锁相环（PLL）系统基于输入参考信号产生振荡器信号。 校准电路产生校准电流，电压 - 电流转换器将控制电压转换成第一电流。 电流控制振荡器基于第一电流和校准电流产生振荡器信号。 连接到相位检测器，电压 - 电流转换器和校准电路的电荷泵电路基于第一电流和校准电流产生电荷泵电流。 电荷泵电流用于根据误差信号产生控制电压。

公开(公告)号：US20110291724A1

公开(公告)日：2011-12-01

申请号：US12786496

申请日：2010-05-25

申请人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinash Chandra Tripathi ,  Sanjay Kumar Wadhwa

发明人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinash Chandra Tripathi ,  Sanjay Kumar Wadhwa

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

摘要翻译： 用于校正由时钟发生器产生的时钟信号的占空比的占空比校正电路包括互补缓冲链，电平移位器电路和自偏置电路。 具有失真占空比的时钟信号及其补码提供给电平移位器电路。 电平移位器电路减小时钟信号和补码的电压幅值，并产生电平移位信号。 电平移位信号被提供给差分放大器，该差分放大器产生指示占空比中的失真幅度的控制信号。 控制信号用于校正时钟信号的占空比。 自偏置电路用于偏置差分放大器。

公开(公告)号：US07907022B2

公开(公告)日：2011-03-15

申请号：US12428490

申请日：2009-04-23

申请人： Krishna Thakur ,  Deependra K Jain ,  Vinod Jain

发明人： Krishna Thakur ,  Deependra K Jain ,  Vinod Jain

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L7/0898 ,  H03L7/10 ,  H03L2207/06

摘要： A phase-locked loop (PLL) system generates an oscillator signal based on an input reference signal. A calibration circuit generates a calibration current, and a voltage-to-current converter converts a control voltage into a first current. A current-controlled oscillator generates the oscillator signal based on the first current and the calibration current. A charge pump circuit, which is connected to a phase detector, the voltage-to-current converter, and the calibration circuit, generates a charge pump current based on the first current and the calibration current. The charge pump current is used to generate the control voltage based on an error signal.

摘要翻译： 锁相环（PLL）系统基于输入参考信号产生振荡器信号。 校准电路产生校准电流，电压 - 电流转换器将控制电压转换成第一电流。 电流控制振荡器基于第一电流和校准电流产生振荡器信号。 连接到相位检测器，电压 - 电流转换器和校准电路的电荷泵电路基于第一电流和校准电流产生电荷泵电流。 电荷泵电流用于根据误差信号产生控制电压。