公开(公告)号：US20080111580A1

公开(公告)日：2008-05-15

申请号：US11897520

申请日：2007-08-30

Applicant: Ankit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

Inventor： Ankit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

IPC: H03K17/16

CPC classification number: H03K17/6872 ,  H03K17/04206 ,  H03K17/0822 ,  H03K17/165

Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract translation: 一种用于在驱动传输线负载的CMOS缓冲器的状态转变期间改善输出的输出缓冲器电路。 电路产生与负载传输线阻抗成比例的可变输出阻抗。 缓冲器包括输出级，例如用于接收输入信号并产生输出信号的上拉/下拉驱动器。 上拉/下拉驱动器由产生控制信号的电路偏置，并根据控制信号改变其电导率。 上拉/下拉驱动器最初提供相对较低的阻抗以在输出的初始过渡期间达到期望的电平，然后响应于控制信号缓慢地改变其阻抗以抑制振铃效应。 控制电路耦合到输入节点，输出节点和电源节点，以产生偏置上拉/下拉驱动器的控制信号。