公开(公告)号：US07299144B2

公开(公告)日：2007-11-20

申请号：US11304141

申请日：2005-12-15

申请人： Roger Allen Booth, Jr. ,  Matthew Stephen Doyle ,  Lynn Robert Landin ,  Thomas W. Liang ,  Ankur Kanu Patel

发明人： Roger Allen Booth, Jr. ,  Matthew Stephen Doyle ,  Lynn Robert Landin ,  Thomas W. Liang ,  Ankur Kanu Patel

IPC分类号： G01D18/00

CPC分类号： G01R35/00

摘要： A method and apparatus are provided for implementing automatic-calibration of a Time Domain Reflectometer (TDR) probing apparatus. A calibration procedure is performed automatically each time a TDR probe is moved from a device under test (DUT). A current calibration TDR waveform is obtained and compared with a reference calibration TDR waveform, checking for deviations between the current and reference measurements. If a deviation is detected, then the user is notified and calibration is failed.

摘要翻译： 提供了一种用于实现时域反射计（TDR）探测装置的自动校准的方法和装置。 每次TDR探针从被测设备（DUT）移动时，都会自动执行校准程序。 获得当前的校准TDR波形并与参考校准TDR波形进行比较，检查电流和参考测量之间的偏差。 如果检测到偏差，则通知用户并校准失败。

公开(公告)号：US07921404B2

公开(公告)日：2011-04-05

申请号：US11954092

申请日：2007-12-11

申请人： Anil Bindu Lingambudi ,  Ankur Kanu Patel ,  Saravanan Sethuraman ,  Diyanesh Vidyapoornachary Babu Chinnakkonda

发明人： Anil Bindu Lingambudi ,  Ankur Kanu Patel ,  Saravanan Sethuraman ,  Diyanesh Vidyapoornachary Babu Chinnakkonda

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file. Finally, the method includes the step of processing the first design constraints output file, the second design constraints output file, and the attribute change file to map constraints associated with changed attributes, thus defining a revised constraints output file for the second design. The revised second constraints output file comprises constraints for at least some signals with changed attributes.

摘要翻译： 公开了一种用于电子处理在先前开发的具有第一约束输出文件的第一PCB设计中定义的约束规则的方法，以便于开发具有第二约束输出文件的第二PCB设计。 第二设计具有与第一设计基本相同的拓扑，第二约束输出文件包括具有相同属性的信号的约束。 该方法包括几个步骤。 首先，将第一设计的板文件与第二设计的网表文件进行比较，以识别设计之间的差异。 在建立的差异的基础上，生成文件属性变更报告。 文件属性更改报告中的至少一些数据将存储到属性更改文件中。 最后，该方法包括处理第一设计约束输出文件，第二设计约束输出文件和属性更改文件以映射与改变的属性相关联的约束的步骤，从而为第二设计定义修改的约束输出文件。 修改的第二约束输出文件包括至少一些具有变化属性的信号的约束。

公开(公告)号：US20090189635A1

公开(公告)日：2009-07-30

申请号：US12020727

申请日：2008-01-28

申请人： Roger Allen Booth, JR. ,  John Richard Dangler ,  Matthew Stephen Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Paul W. Rudrud

发明人： Roger Allen Booth, JR. ,  John Richard Dangler ,  Matthew Stephen Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Paul W. Rudrud

IPC分类号： H03K19/003

CPC分类号： H03K5/084 ,  H03K5/003 ,  H03K5/151

摘要： A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).

摘要翻译： 一种方法和装置实现了对单端时钟的降低的噪声耦合效应，并且提供了主题电路所在的设计结构。 时钟接收器包括从接收到的输入时钟信号的接收时钟峰值和谷值产生的时钟参考电压。 接收的时钟峰值（VT）和接收时钟谷（VB）被连续采样。 时钟电压基准设置为例如等于VT和VB的平均值; 或（（VT + VB）/ 2）。

公开(公告)号：US07353130B2

公开(公告)日：2008-04-01

申请号：US11781372

申请日：2007-07-23

申请人： Roger Allen Booth, Jr. ,  Matthew Stephen Doyle ,  Lynn Robert Landin ,  Thomas W. Liang ,  Ankur Kanu Patel

发明人： Roger Allen Booth, Jr. ,  Matthew Stephen Doyle ,  Lynn Robert Landin ,  Thomas W. Liang ,  Ankur Kanu Patel

IPC分类号： G01R35/00

CPC分类号： G01R35/00

摘要： A method and apparatus are provided for implementing automatic-calibration of a Time Domain Reflectometer (TDR) probing apparatus. A calibration procedure is performed automatically each time a TDR probe is moved from a device under test (DUT). A current calibration TDR waveform is obtained and compared with a reference calibration TDR waveform, checking for deviations between the current and reference measurements. If a deviation is detected, then the user is notified and calibration is failed.

摘要翻译： 提供了一种用于实现时域反射计（TDR）探测装置的自动校准的方法和装置。 每次TDR探针从被测设备（DUT）移动时，都会自动执行校准程序。 获得当前的校准TDR波形并与参考校准TDR波形进行比较，检查电流和参考测量之间的偏差。 如果检测到偏差，则通知用户并校准失败。

公开(公告)号：US07235875B2

公开(公告)日：2007-06-26

申请号：US11008798

申请日：2004-12-09

申请人： Roger Allen Booth, Jr. ,  Matthew Stephen Doyle ,  Don Alan Gilliland ,  Brian Edward Gregg ,  Lynn Robert Landin ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Dennis James Wurth

发明人： Roger Allen Booth, Jr. ,  Matthew Stephen Doyle ,  Don Alan Gilliland ,  Brian Edward Gregg ,  Lynn Robert Landin ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Dennis James Wurth

IPC分类号： H01L23/10 ,  H01L29/06

CPC分类号： H05K1/0231 ,  H01L23/3672 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K3/301 ,  H05K2201/10454 ,  H05K2201/2018 ,  H01L2924/00

摘要： A modular heat sink decoupling capacitor array includes a plurality of modules, each defining parallel distributed decoupling plates, and each module forming a heat sink fi. Each module includes multiple spaced apart contacts for providing low inductance connections with an associated device. A power distribution interposer module is attached to a heat sink surface of the modular decoupling capacitor. The interposer module is used for implementing power delivery without using valuable ball grid array (BGA) connections and printed circuit board (PCB) layers.

摘要翻译： 模块化散热器去耦电容器阵列包括多个模块，每个模块限定平行分布式去耦板，并且每个模块形成散热片fi。 每个模块包括多个间隔开的触点，用于与相关联的装置提供低电感连接。 功率分配插入器模块连接到模块化去耦电容器的散热器表面。 内插器模块用于实现功率输送，而不使用有价值的球栅阵列（BGA）连接和印刷电路板（PCB）层。

公开(公告)号：US20090150834A1

公开(公告)日：2009-06-11

申请号：US11954092

申请日：2007-12-11

申请人： Anil Bindu Lingambudi ,  Ankur Kanu Patel ,  Saravanan Sethuraman ,  Diyanesh Vidyapoornachary Babu Chinnakkonda

发明人： Anil Bindu Lingambudi ,  Ankur Kanu Patel ,  Saravanan Sethuraman ,  Diyanesh Vidyapoornachary Babu Chinnakkonda

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file. Finally, the method includes the step of processing the first design constraints output file, the second design constraints output file, and the attribute change file to map constraints associated with changed attributes, thus defining a revised constraints output file for the second design. The revised second constraints output file comprises constraints for at least some signals with changed attributes.

摘要翻译： 公开了一种用于电子处理在先前开发的具有第一约束输出文件的第一PCB设计中定义的约束规则的方法，以便于开发具有第二约束输出文件的第二PCB设计。 第二设计具有与第一设计基本相同的拓扑，第二约束输出文件包括具有相同属性的信号的约束。 该方法包括几个步骤。 首先，将第一设计的板文件与第二设计的网表文件进行比较，以识别设计之间的差异。 在建立的差异的基础上，生成文件属性变更报告。 文件属性更改报告中的至少一些数据将存储到属性更改文件中。 最后，该方法包括处理第一设计约束输出文件，第二设计约束输出文件和属性更改文件以映射与改变的属性相关联的约束的步骤，从而为第二设计定义修改的约束输出文件。 修改的第二约束输出文件包括至少一些具有变化属性的信号的约束。