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    Controlling impedance and thickness variations for multilayer electronic structures
    1.
    发明授权
    Controlling impedance and thickness variations for multilayer electronic structures 有权
    控制多层电子结构的阻抗和厚度变化

    公开(公告)号：US07921403B2

    公开(公告)日：2011-04-05

    申请号：US12101455

    申请日：2008-04-11

    申请人： John Richard Dangler ,  Matthew Stephen Doyle

    发明人： John Richard Dangler ,  Matthew Stephen Doyle

    IPC分类号： G06F17/50 ,  H03K17/693 ,  H05K1/00 ,  H05K1/09

    CPC分类号： H05K1/024 ,  G06F17/5018 ,  H01P11/003 ,  H05K1/0298 ,  H05K3/0005 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09881 ,  H05K2203/063

    摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

    摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 当前的现有技术设计和制造工艺本身将物理电介质厚度变化引入PCB横截面。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了产生均衡数据的过程和用于多层电子结构的设计结构。

    Controlling Impedance and Thickness Variations for Multilayer Electronic Structures
    2.
    发明申请
    Controlling Impedance and Thickness Variations for Multilayer Electronic Structures 有权
    控制多层电子结构的阻抗和厚度变化

    公开(公告)号：US20090255713A1

    公开(公告)日：2009-10-15

    申请号：US12101455

    申请日：2008-04-11

    申请人： John Richard Dangler ,  Matthew Stephen Doyle

    发明人： John Richard Dangler ,  Matthew Stephen Doyle

    IPC分类号： H05K1/00 ,  G06F17/50

    CPC分类号： H05K1/024 ,  G06F17/5018 ,  H01P11/003 ,  H05K1/0298 ,  H05K3/0005 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09881 ,  H05K2203/063

    摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

    摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 当前的现有技术设计和制造工艺本身将物理电介质厚度变化引入PCB横截面。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了产生均衡数据的过程和用于多层电子结构的设计结构。

    Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications
    6.
    发明授权
    Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications 失效
    用于高速柔性电路应用中特征阻抗不连续性降低的方法和装置

    公开(公告)号：US07308661B2

    公开(公告)日：2007-12-11

    申请号：US11008812

    申请日：2004-12-09

    申请人： Matthew Stephen Doyle

    发明人： Matthew Stephen Doyle

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5018 ,  H05K1/0393 ,  H05K3/0005

    摘要： A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a user defined delta value. If the compared areas differ greater than the user defined delta value, then a coordinate change is computed for moving the signal wire to reduce characteristic impedance discontinuity.

    摘要翻译： 提供了一种用于在定制的高速柔性电路应用中实现特征阻抗不连续性降低的方法和装置。 选择一个弧形的艺术品区域，并扫描所选的单元格。 确定每个单元内的信号线的相对侧上的区域。 使用用户定义的增量值比较识别的区域。 如果比较区域差异大于用户定义的增量值，则计算移动信号线的坐标变化以减小特征阻抗不连续性。

    Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications
    7.
    发明申请
    Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications 失效
    用于高速柔性电路应用中特征阻抗不连续性降低的方法和装置

    公开(公告)号：US20060129965A1

    公开(公告)日：2006-06-15

    申请号：US11008812

    申请日：2004-12-09

    申请人： Matthew Stephen Doyle

    发明人： Matthew Stephen Doyle

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5045 ,  G06F17/5018 ,  H05K1/0393 ,  H05K3/0005

    摘要： A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a user defined delta value. If the compared areas differ greater than the user defined delta value, then a coordinate change is computed for moving the signal wire to reduce characteristic impedance discontinuity.

    摘要翻译： 提供了一种用于在定制的高速柔性电路应用中实现特征阻抗不连续性降低的方法和装置。 选择一个弧形的艺术品区域，并扫描所选的单元格。 确定每个单元内的信号线的相对侧上的区域。 使用用户定义的增量值比较识别的区域。 如果比较区域差异大于用户定义的增量值，则计算移动信号线的坐标变化以减小特征阻抗不连续性。

    Controlling impedance and thickness variations for multilayer electronic structures
    8.
    发明授权
    Controlling impedance and thickness variations for multilayer electronic structures 失效
    控制多层电子结构的阻抗和厚度变化

    公开(公告)号：US08549444B2

    公开(公告)日：2013-10-01

    申请号：US12101441

    申请日：2008-04-11

    申请人： John Richard Dangler ,  Matthew Stephen Doyle

    发明人： John Richard Dangler ,  Matthew Stephen Doyle

    IPC分类号： G06F17/50 ,  H05K1/00 ,  H05K1/03

    CPC分类号： H05K1/024 ,  H01P11/003 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09881 ,  H05K2203/063

    摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

    摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 现有技术的设计和制造工艺现在将物理电介质厚度变化引入到多层横截面中。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了多层结构和制造方法。