公开(公告)号：US20080211530A1

公开(公告)日：2008-09-04

申请号：US12103906

申请日：2008-04-16

申请人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

发明人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

公开(公告)号：US20080211531A1

公开(公告)日：2008-09-04

申请号：US12119834

申请日：2008-05-13

申请人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

发明人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/3008 ,  G01R31/31858

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

公开(公告)号：US06618682B2

公开(公告)日：2003-09-09

申请号：US09838996

申请日：2001-04-20

申请人： Raymond J. Bulaga ,  Anne E. Gattiker ,  John L. Harris ,  Phillip J. Nigh ,  Leo A. Noel ,  William J. Thibault ,  Jody J. Van Horn ,  Donald L. Wheater

发明人： Raymond J. Bulaga ,  Anne E. Gattiker ,  John L. Harris ,  Phillip J. Nigh ,  Leo A. Noel ,  William J. Thibault ,  Jody J. Van Horn ,  Donald L. Wheater

IPC分类号： G01N3700

CPC分类号： H01L22/20

摘要： A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

公开(公告)号：US20080284459A1

公开(公告)日：2008-11-20

申请号：US12185151

申请日：2008-08-04

申请人： Anne E. Gattiker ,  Phil Nigh ,  Leah M. P. Pastel ,  Steven F. Oakland ,  Jody VanHorn ,  Paul S. Zuchowski

发明人： Anne E. Gattiker ,  Phil Nigh ,  Leah M. P. Pastel ,  Steven F. Oakland ,  Jody VanHorn ,  Paul S. Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318575 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.

摘要翻译： 一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。 该架构包括多个电压岛，每个电压岛由相应的岛源电压供电，以及耦合到电压岛的测试电路，并由在测试期间始终导通的全局源电压供电，其中每个岛源电压可以是 在测试期间独立控制。

公开(公告)号：US07428675B2

公开(公告)日：2008-09-23

申请号：US10545961

申请日：2003-02-20

申请人： Anne E. Gattiker ,  Phil Nigh ,  Leah M. P. Pastel ,  Steven F. Oakland ,  Jody VanHorn ,  Paul S. Zuchowski

发明人： Anne E. Gattiker ,  Phil Nigh ,  Leah M. P. Pastel ,  Steven F. Oakland ,  Jody VanHorn ,  Paul S. Zuchowski

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318575 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.

摘要翻译： 一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。 该架构包括多个电压岛（102,104），每个电压岛由相应的岛源电压（VDDI 1，VDDI 2）供电，以及耦合到电压岛的测试电路（116），并由全局源 在测试期间总是导通的电压（Vg），其中每个岛源电压可以在测试期间被独立地控制（106,108）。

公开(公告)号：US07759960B2

公开(公告)日：2010-07-20

申请号：US12103906

申请日：2008-04-16

申请人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

发明人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。