公开(公告)号：US08589835B2

公开(公告)日：2013-11-19

申请号：US13433395

申请日：2012-03-29

申请人： Anshuman Nayak ,  Samantak Chakrabarti ,  Brijesh Agrawal ,  Nitin Bhardwaj

发明人： Anshuman Nayak ,  Samantak Chakrabarti ,  Brijesh Agrawal ,  Nitin Bhardwaj

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.

摘要翻译： 公开了用于从注册传输级（RTL）网表推断电路连接的更高级别描述的系统和方法，以便为复杂的片上系统（SOC）设计提供更易于理解和可管理的设计描述。 特别地，基于规则的接口匹配通过分析功能元件和块的实例上的实际端口名称来自动执行，以形成包含更高级抽象描述的信号分组。 提供了一个示例语法来定义用于定义如何执行各种分析的规则。 可选地提供了描述共同知识产权（IP）块的标准接口的数据，以便于接口匹配。 此外，还包括一个工具，以便在RTL级别设计中实现与实际端口名称相关的实例化接口上的用户指导映射。

公开(公告)号：US20130185682A1

公开(公告)日：2013-07-18

申请号：US13433395

申请日：2012-03-29

申请人： Anshuman NAYAK ,  Samantak CHAKRABARTI ,  Brijesh AGRAWAL ,  Nitin Bhardwaj

发明人： Anshuman NAYAK ,  Samantak CHAKRABARTI ,  Brijesh AGRAWAL ,  Nitin Bhardwaj

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.

摘要翻译： 公开了用于从注册传输级（RTL）网表推断电路连接的更高级别描述的系统和方法，以便为复杂的片上系统（SOC）设计提供更易于理解和可管理的设计描述。 特别地，基于规则的接口匹配通过分析功能元件和块的实例上的实际端口名称来自动执行，以形成包含更高级抽象描述的信号分组。 提供了一个示例语法来定义用于定义如何执行各种分析的规则。 可选地提供了描述共同知识产权（IP）块的标准接口的数据，以便于接口匹配。 此外，还包括一个工具，以便在RTL级别设计中实现与实际端口名称相关的实例化接口上的用户指导映射。

公开(公告)号：US20080244472A1

公开(公告)日：2008-10-02

申请号：US11692949

申请日：2007-03-29

申请人： Anshuman NAYAK ,  Samantak CHAKRABARTI ,  Satrajit PAL ,  Hitanshu DEWAN

发明人： Anshuman NAYAK ,  Samantak CHAKRABARTI ,  Satrajit PAL ,  Hitanshu DEWAN

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method for accelerating the generation of an optimized netlist from a RTL representation is provided. The method optimizes a given RTL description of an integrated circuit (IC) design by: generating a static single assignment (SSA) graph; creating value range propagation for each variable in the SSA graph; and, applying one or more of a set of optimization algorithms on the SSA graph. The optimization algorithms include, but are not limited to, dead-code elimination, bitwidth analysis, redundancy elimination, iteration loop optimization, algebraic simplification and so on. These algorithms operate on a word-level description to enable fast optimization. Furthermore, the optimized RTL accelerates the overall flow of an IC design.

摘要翻译： 提供了一种用于从RTL表示加速优化网表的生成的方法。 该方法通过以下方式优化集成电路（IC）设计的给定RTL描述：生成静态单赋值（SSA）图; 为SSA图中的每个变量创建值范围传播; 并且在SSA图上应用一组优化算法中的一个或多个。 优化算法包括但不限于死码消除，位宽分析，冗余消除，迭代循环优化，代数简化等。 这些算法在字级描述上运行，以实现快速优化。 此外，优化的RTL加速了IC设计的整体流程。

公开(公告)号：US08656335B2

公开(公告)日：2014-02-18

申请号：US13532175

申请日：2012-06-25

申请人： Anshuman Nayak ,  Samantak Chakrabarti ,  Brijesh Agrawal ,  Nitin Bhardwaj

发明人： Anshuman Nayak ,  Samantak Chakrabarti ,  Brijesh Agrawal ,  Nitin Bhardwaj

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045

摘要： A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.

摘要翻译： 提供了一种用于从注册传输级（RTL）网表推断电路连接的更高级别描述的系统和几种方法，以便为复杂的片上系统（SOC）设计提供更易于理解和可管理的设计描述。 特别地，自动执行基于连接传播的接口匹配，从而将功能元件和块的实例上的端口名称和属性传播到顶级设计端口以及功能元件和块的其他实例，以创建更稳健的连接描述 到RTL网表，并自动形成包含更高级抽象描述的信号分组。 此外，还包括一个工具，以允许用户指导对RTL级设计中的实际信号名称和属性对实例化接口进行分组。

公开(公告)号：US20130290917A1

公开(公告)日：2013-10-31

申请号：US13532175

申请日：2012-06-25

申请人： Anshuman NAYAK ,  Samantak CHAKRABARTI ,  Brijesh AGRAWAL ,  Nitin BHARDWAJ

发明人： Anshuman NAYAK ,  Samantak CHAKRABARTI ,  Brijesh AGRAWAL ,  Nitin BHARDWAJ

IPC分类号： G06F9/45

CPC分类号： G06F17/5081 ,  G06F17/5045

摘要： A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.

摘要翻译： 提供了一种用于从注册传输级（RTL）网表推断电路连接的更高级别描述的系统和几种方法，以便为复杂的片上系统（SOC）设计提供更易于理解和可管理的设计描述。 特别地，自动执行基于连接传播的接口匹配，从而将功能元件和块的实例上的端口名称和属性传播到顶级设计端口以及功能元件和块的其他实例，以创建更稳健的连接描述 到RTL网表，并自动形成包含更高级抽象描述的信号分组。 此外，还包括一个工具，以允许用户指导对RTL级设计中的实际信号名称和属性对实例化接口进行分组。

公开(公告)号：US07376939B1

公开(公告)日：2008-05-20

申请号：US10072212

申请日：2002-02-07

申请人： Anshuman Nayak ,  Malay Haldar ,  Alok Choudhary ,  Vikram Saxena ,  Prithviraj Banerjee

发明人： Anshuman Nayak ,  Malay Haldar ,  Alok Choudhary ,  Vikram Saxena ,  Prithviraj Banerjee

IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F17/50 ,  G06F7/62 ,  G06F9/44

CPC分类号： G06F17/5045 ,  G06F17/5031

摘要： Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.

摘要翻译： 电子设计自动化工具规定了系统级及其组件（包括嵌入式处理器，算术逻辑单元（ALU），乘法器，分频器，嵌入式存储器元件，可编程逻辑单元等）的知识产权（IP）内核的架构。 指定IP内核及其接口; 并通过其界面了解IP内核和功能。 此外，提供了用于对功能或功能块的定时行为建模而不绘制时序图的技术; 了解捕获时序波形的功能块的接口行为; 指定使用基本功能单元构建的虚拟功能及其时序行为; 解析和创建用于分析编译规范的内部图形表单; 匹配架构规范中的组件及其实例化以映射从应用程序生成的输入图中的计算; 并将规范映射到目标的组件上。

公开(公告)号：US07000213B2

公开(公告)日：2006-02-14

申请号：US09770541

申请日：2001-01-26

申请人： Prithviraj Banerjee ,  Alok Choudhary ,  Malay Haldar ,  Anshuman Nayak

发明人： Prithviraj Banerjee ,  Alok Choudhary ,  Malay Haldar ,  Anshuman Nayak

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F8/4434 ,  G06F8/445 ,  G06F17/5045

摘要： Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.

摘要翻译： 数字电路由MATLAB编程语言中描述的算法合成。 一个MATLAB程序被编译成RTL-VHDL，它可以使用特定于系统的工具来开发ASIC或FPGA配置。 执行中间变换和优化，以获得给定MATLAB程序的RTL-VHDL或RTL Verilog中的高度优化的描述。 优化包括级别化，标量化，流水线化，类型形状分析，内存优化，精确分析和调度。