公开(公告)号：US5598184A

公开(公告)日：1997-01-28

申请号：US859213

申请日：1992-03-27

申请人： Anthony C. Barkans

发明人： Anthony C. Barkans

IPC分类号： G09G5/00 ,  G06T5/00 ,  G06T5/20 ,  G09G3/20 ,  G09G5/02 ,  G09G5/04 ,  H04N7/26 ,  G09G5/10

CPC分类号： G09G5/02 ,  H04N19/90 ,  G09G3/2051

摘要： Color information lost in a computer graphics system as a result of encoding by dithering is recovered by passing the encoded data through a filter that has the same effective shape and size as the dither matrix used to encode the data. In a system that employs a dither matrix having 2.sup.N cells, up to N bits of color information, per color component, is recoverable.

摘要翻译： 作为通过抖动进行编码的结果，在计算机图形系统中丢失的颜色信息通过将编码数据通过与用于编码数据的抖动矩阵具有相同有效形状和大小的滤波器来恢复。 在采用具有2N个单元的抖动矩阵的系统中，每个颜色分量多达N位的颜色信息是可恢复的。

公开(公告)号：US5929862A

公开(公告)日：1999-07-27

申请号：US692350

申请日：1996-08-05

申请人： Anthony C. Barkans

发明人： Anthony C. Barkans

IPC分类号： G06T11/00 ,  G06F15/00

CPC分类号： G06T11/40

摘要： An antialiasing system is implemented in a graphics system of a computer. A memory control is associated with graphics system for controlling a frame buffer. The antialiasing system is situated in the memory control and is configured to receive from steppers (edge and span) new color values and new depth dimensions z at a plurality of subpixel locations. In turn, the antialiasing system analyzes color data pertaining to each pixel in the frame buffer, and if necessary, updates the color data. The color data is unique and minimizes memory requirements and accesses. Specifically, the color data includes a current display value that corresponds to the pixel, a reference color value that corresponds to one subpixel location, a reference depth dimension that corresponds with the one subpixel location, and reconstruction indicia that correspond with other subpixel locations and that can be utilized to derive respective depth dimensions and colors for the other subpixel locations. The reconstruction indicia include a hint and a depth dimension difference. The hint indicates color informationm, and the depth dimension difference represents a difference between the reference depth dimension and a respective depth dimension.

摘要翻译： 在计算机的图形系统中实现了抗混叠系统。 存储器控制与用于控制帧缓冲器的图形系统相关联。 抗混叠系统位于存储器控制中，并被配置为从多个子像素位置处的步进器（边缘和跨度）接收新的颜色值和新的深度尺寸z。 反锯齿系统又分析与帧缓冲器中的每个像素有关的颜色数据，如果需要，更新颜色数据。 颜色数据是唯一的，并最大限度地减少内存需求和访问。 具体地，颜色数据包括对应于像素的当前显示值，对应于一个子像素位置的参考颜色值，对应于一个子像素位置的参考深度尺寸，以及与其他子像素位置相对应的重建标记，并且 可用于导出其他子像素位置的相应深度尺寸和颜色。 重建标记包括提示和深度维度差异。 提示表示颜色信息m，深度尺寸差表示参考深度尺寸和相应深度尺寸之间的差异。

公开(公告)号：US4988985A

公开(公告)日：1991-01-29

申请号：US384877

申请日：1989-07-24

申请人： Anthony C. Barkans ,  Jorge Lach

发明人： Anthony C. Barkans ,  Jorge Lach

IPC分类号： G09G5/393

CPC分类号： G09G5/393

摘要： A three-dimensional frame-buffer memory organized into a series of planes each storing one bit representative of a pixel on the display can draw a figure onto one of the planes. The figure can then be copied to preselected ones of the other planes while the first plane is cleared. A bit block transfer can be performed from an "invisible" portion of the first plane to pre-selected ones of the other planes.

摘要翻译： 组织成一系列平面的三维帧缓冲存储器可以在一个平面上绘制一个图形，每个平面都存储一个代表像素的位， 然后可以在第一个平面被清除时将该图复制到其他平面中的预选的其他平面。 可以从第一平面的“不可见”部分到其他平面中的预先选择的一个执行位块传送。

公开(公告)号：US6057855A

公开(公告)日：2000-05-02

申请号：US887441

申请日：1997-07-02

申请人： Anthony C Barkans

发明人： Anthony C Barkans

IPC分类号： G06T11/20 ,  G06T11/00 ,  G06T11/60

CPC分类号： G06T11/40 ,  G06T11/001 ,  G06T2200/12

摘要： A method and apparatus for generating a mask identifying a number of subpixels that are covered by a primitive includes the process of apportioning an image, comprising a plurality of scan lines into a plurality of sub-scan lines, such that a number of sub-scan lines crosses each pixel. A sample point is placed on at least one of the sub-scan lines. To determine the number of samples that are covered by a primitive, edge stepping is used to step along each edge of the primitive, generating a sub-scan line coordinate for the edge. The edge stepping hardware is used for stepping either on a sub-scan line granularity, for operation in anti-aliased mode, or on a scan line granularity, for operation in aliased mode. In anti-aliased mode, as each edge sub-scan line coordinate is generated, it is compared against the coordinates of a sample point on that sub-scan line, to determine whether or not that sample point is covered by the primitive. A mask is generated for each pixel, with each bit of the mask corresponding to one of the sub-scan line samples. A bit in the mask is set if the subsample is covered by the primitive. Thus, a mask representing covered subsamples is provided by using incremental techniques to approximate pixel coverage without the complex hardware and lookup tables used in the prior art.

摘要翻译： 一种用于产生识别由图元覆盖的子像素数目的掩模的方法和装置包括将包括多条扫描线的图像分配到多个子扫描线中的过程，使得多个子扫描 线穿过每个像素。 采样点放置在至少一个副扫描线上。 为了确定由原语覆盖的样本数，边缘步长用于沿着图元的每个边缘，沿边缘生成子扫描线坐标。 边缘步进硬件用于在子扫描线粒度上进行步进，以抗锯齿模式运行，或者以扫描线粒度进行步进，以在混叠模式下运行。 在抗混叠模式中，当生成每个边缘子扫描线坐标时，将其与该子扫描线上的采样点的坐标进行比较，以确定该采样点是否被图元覆盖。 对于每个像素生成掩模，掩模的每个位对应于子扫描线样本之一。 如果子样本被原语覆盖，则掩码中的一点被设置。 因此，通过使用增量技术来提供表示覆盖的子样本的掩码以近似像素覆盖，而不需要现有技术中使用的复杂硬件和查找表。

公开(公告)号：US5905504A

公开(公告)日：1999-05-18

申请号：US770073

申请日：1996-12-19

申请人： Anthony C. Barkans ,  David L. McAllister

发明人： Anthony C. Barkans ,  David L. McAllister

IPC分类号： H04N1/52 ,  G06T5/00 ,  G09G5/02 ,  H04N1/64 ,  G06T5/20

CPC分类号： H04N1/648

摘要： A color graphics pipeline has a separate encoder with a dither table for processing each color value in pixel data received from a host processor or rasterizer. The encoders modify color values and dither noise values and also combine both positive and negative dither noise values with the color values, for independent optimization of each color and for better edge detection in a color recovery filter within a decoder of the pipeline. Each encoder comprises the following elements. A comparator mechanism compares a color value with a predetermined cutoff value. A dither table provides dither noise values. An offset mechanism modifies the dither noise values to derive a modified dither noise value when the color value is greater than or equal to the predetermined cutoff value. An aliasing mechanism aliases the color value with other color values below the predetermined cutoff value to derive an aliased color value when the color value is less than the predetermined cutoff value. An adder mechanism adds the unmodified dither noise or modified dither noise to the aliased color value or nonaliased color value, respectively, to derive the dithered color value. A clamping mechanism ensures that the dithered color value resides within a predetermined color range. Finally, a quantizing mechanism quantizes the dithered color value to derive a quantized/dithered color value for storage in memory, such as in a frame buffer.

摘要翻译： 彩色图形管线具有单独的编码器，其具有用于处理从主处理器或光栅化器接收的像素数据中的每个颜色值的抖动表。 编码器修改颜色值和抖动噪声值，并且将正和负抖动噪声值与颜色值组合，用于各种颜色的独立优化，以及在管道解码器内的色彩恢复滤波器中更好的边缘检测。 每个编码器包括以下元件。 比较器机构将颜色值与预定的截止值进行比较。 抖动表提供抖动噪声值。 当颜色值大于或等于预定截止值时，偏移机构修改抖动噪声值以导出修改的抖动噪声值。 混叠机制使颜色值与预定截止值以下的其他颜色值相差，以便当颜色值小于预定截止值时导出混叠色值。 加法器机构将未修改的抖动噪声或修改的抖动噪声分别添加到别名颜色值或非混合颜色值，以导出抖动颜色值。 夹持机构确保抖动色值驻留在预定的颜色范围内。 最后，量化机制量化抖动颜色值以导出用于存储在存储器中的量化/抖动颜色值，例如在帧缓冲器中。

公开(公告)号：US5519822A

公开(公告)日：1996-05-21

申请号：US354171

申请日：1994-12-09

申请人： Anthony C. Barkans ,  Bryan G. Prouty ,  Lawrence G. Mahoney ,  Ian A. Elliott

发明人： Anthony C. Barkans ,  Bryan G. Prouty ,  Lawrence G. Mahoney ,  Ian A. Elliott

IPC分类号： G09G5/20 ,  G06T11/20 ,  G06F15/62

CPC分类号： G06T11/203

摘要： First next and second next pixel locations are selected simultaneously from among adjacent pixel locations and represent a straight line segment defined by two end locations and having a slope of one or less. An initialization process uses the .DELTA.X and .DELTA.Y of the desired line segment to find various constants, including an initial error term, an error term increment, an error term decrement, an error term double increment, an error term double decrement, and an error term increment-then-decrement. These represent, respectively, an increment in the X location without an increment to the Y location (a step S), an increment in the X location and an increment in the Y location (a jump J), a step followed by a step (two steps SS), two jumps (JJ), and either of a step-then-jump or a jump-then-step (SJ/JS). These five operations correspond to the only possible locations that might be selected, given any starting location. Of the five operations, exactly one of the first two will be for the first next location, while exactly one of the last three will be for the second next location. The present error term is an input to three different adders. Another input to each of the adders is one of the constants for S or J and two of the constants for SS, JJ and SJ/JS. The three additions proceed simultaneously. The initial error term and the resulting three trial error terms can be inspected in relation to error term limits. When the Bresenham Algorithm is implemented, these comparisons are simple determinations of sign. A logic circuit responsive to the error term inspection indicates which combination of the operations S and J correspond to the desired path. A corresponding frame buffer operation code is sent to the a frame buffer address controller. Once the selection is made the error term value for the selected second next pixel location is captured and made to be the error term input for the adders, and the process is ready to select another two pixel locations. If .DELTA.X is an odd number then the second next position is not needed for the final sequence of frame buffer operation codes, and it to be suppressed.

公开(公告)号：US5428810A

公开(公告)日：1995-06-27

申请号：US220948

申请日：1994-03-31

申请人： Anthony C. Barkans ,  Roger Swanson

发明人： Anthony C. Barkans ,  Roger Swanson

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3867

摘要： A technique of processing pipeline commands in parallel so as to minimize pipeline stalls. This is accomplished in accordance with the invention without need for the complex resource allocation techniques of the prior art by arbitrating access to critical pipeline resources on the phase of the system clock. For example, one control process may access the critical pipeline resource only during an even phase of the system clock, while a second control process may access the critical pipeline resource only during the odd phase of the clock. These processes may run at the same time if the pipelined instructions being executed by each process have no data dependencies since structural hazards are effectively eliminated by time-sharing the data buses on the respective phases of the system clock. The benefits of dynamically scheduled pipelined systems may thus be obtained without the complex scoreboarding and other scheduling algorithms used in the prior art to prevent pipeline hazards.

摘要翻译： 并行处理流水线命令的技术，以最大限度地减少管道停顿。 这是根据本发明完成的，而不需要现有技术的复杂资源分配技术，通过在系统时钟的相位上仲裁对关键流水线资源的访问。 例如，一个控制过程只能在系统时钟的偶数阶段期间访问关键流水线资源，而第二个控制过程只能在时钟的奇数阶段访问关键流水线资源。 如果由每个进程执行的流水线指令没有数据依赖性，则这些进程可以同时运行，因为通过在系统时钟的各个相位上共享数据总线来有效地消除结构危害。 因此可以获得动态调度流水线系统的好处，而不需要现有技术中使用的复杂记分板和其他调度算法来防止管道危险。

公开(公告)号：US5220650A

公开(公告)日：1993-06-15

申请号：US644188

申请日：1991-01-22

申请人： Anthony C. Barkans

发明人： Anthony C. Barkans

IPC分类号： G06F15/16

CPC分类号： G06F15/16

摘要： A scan conversion algorithm for rendering antialiased vectors in a multi-processor graphics system comprises the following steps: providing signals to the processors indicative of scan lines the respective processors are responsible for, determining a first set of storage pixels to be rendered by the processors, rendering such storage pixel of the first set simultaneously, each by a different processor, determining a second set of storage pixels to be rendered, and rendering each of the second set of storage pixels substantially simultaneously by a different one of the processors. The determinations of the first and second sets of storage pixels are made in accordance with the signals indicative of scan lines for which the respective processors are responsible.

摘要翻译： 用于在多处理器图形系统中渲染抗锯齿矢量的扫描转换算法包括以下步骤：向处理器提供指示各个处理器负责的扫描线的信号，确定由处理器呈现的第一组存储像素， 同时渲染第一组的这样的存储像素，每个由不同的处理器确定要被渲染的第二组存储像素，并且通过不同的处理器基本上同时渲染第二组存储像素中的每一个。 第一组和第二组存储像素的确定根据指示相应处理器负责的扫描线的信号进行。

公开(公告)号：US5649083A

公开(公告)日：1997-07-15

申请号：US228472

申请日：1994-04-15

申请人： Anthony C. Barkans ,  David L. McAllister

发明人： Anthony C. Barkans ,  David L. McAllister

IPC分类号： H04N1/52 ,  G06T5/00 ,  G09G5/02 ,  H04N1/64 ,  G06T5/20

CPC分类号： H04N1/648

摘要： A color graphics pipeline has a separate encoder with a dither table for processing each color value in pixel data received from a host processor or rasterizer. The encoders modify color values and dither noise values and also combine both positive and negative dither noise values with the color values, for independent optimization of each color and for better edge detection in a color recovery filter within a decoder of the pipeline. Each encoder comprises the following elements. A comparator mechanism compares a color value with a predetermined cutoff value. A dither table provides dither noise values. An offset mechanism modifies the dither noise values to derive a modified dither noise value when the color value is greater than or equal to the predetermined cutoff value. An aliasing mechanism aliases the color value with other color values below the predetermined cutoff value to derive an aliased color value when the color value is less than the predetermined cutoff value. An adder mechanism adds the unmodified dither noise or modified dither noise to the aliased color value or nonaliased color value, respectively, to derive the dithered color value. A clamping mechanism ensures that the dithered color value resides within a predetermined color range. Finally, a quantizing mechanism quantizes the dithered color value to derive a quantized/dithered color value for storage in memory, such as in a frame buffer.

摘要翻译： 彩色图形管线具有单独的编码器，其具有用于处理从主处理器或光栅化器接收的像素数据中的每个颜色值的抖动表。 编码器修改颜色值和抖动噪声值，并且将正和负抖动噪声值与颜色值组合，用于各种颜色的独立优化，以及在管道解码器内的色彩恢复滤波器中更好的边缘检测。 每个编码器包括以下元件。 比较器机构将颜色值与预定的截止值进行比较。 抖动表提供抖动噪声值。 当颜色值大于或等于预定截止值时，偏移机构修改抖动噪声值以导出修改的抖动噪声值。 混叠机制使颜色值与预定截止值以下的其他颜色值相差，以便当颜色值小于预定截止值时导出混叠色值。 加法器机构将未修改的抖动噪声或修改的抖动噪声分别添加到别名颜色值或非混合颜色值，以导出抖动颜色值。 夹持机构确保抖动色值驻留在预定的颜色范围内。 最后，量化机制量化抖动颜色值以导出用于存储在存储器中的量化/抖动颜色值，例如在帧缓冲器中。

公开(公告)号：US5519823A

公开(公告)日：1996-05-21

申请号：US371663

申请日：1995-01-11

申请人： Anthony C. Barkans

发明人： Anthony C. Barkans

IPC分类号： G06T11/00 ,  G09G5/20 ,  G06F15/62

CPC分类号： G06T11/203 ,  G09G5/20

摘要： A color/texture interpolator (CTI) for use in rendering antialiased vectors in a computer graphics system comprises: an x-stepper circuit for receiving input data defining a vector to be rendered and generating respective pixel addresses of pixels composing the vector; a filter memory for storing predetermined filter values addressed according to the vector's minor axis subpixel addresses and slope; and a color interpolator for generating a color value for each pixel composing the vector.

摘要翻译： 用于在计算机图形系统中渲染抗锯齿矢量的颜色/纹理内插器（CTI）包括：x步进电路，用于接收定义要渲染的矢量的输入数据，并产生构成矢量的像素的相应像素地址; 滤波器存储器，用于存储根据向量的短轴子像素地址和斜率寻址的预定滤波器值; 以及颜色内插器，用于为构成矢量的每个像素生成颜色值。