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1.发明授权Fast multilevel hierarchical routing table lookup using content addressable memory 失效使用内容可寻址内存的快速多级分层路由表查找
公开(公告)号：US5386413A
公开(公告)日：1995-01-31
申请号：US34444
申请日：1993-03-19
IPC分类号： H04L12/715 , H04Q3/00 , H04Q11/00 , H04L12/56
CPC分类号： H04L45/04 , H04Q3/0016
摘要： A switch memory 100 for implementing a multilevel hierarchical routing table in a switch is disclosed. The switch memory 100 includes a plurality of mask circuits 120, 121 and 122, which each correspond to one level of the multilevel hierarchy. Each mask circuit 120, 121 and 122 receives a destination address of an incoming call or packet and masks out portions of the received destination address which do not correspond to the level of the hierarchy with which the mask circuit 120, 121 or 122 is associated. A memory array 130, 131 or 132 corresponding to each mask circuit 120, 121 or 122, is provided which is capable of storing a table of entries including an output port entry and a corresponding destination address of one level of the multilevel hierarchy of destination addresses. Additionally, each memory array 130, 131 or 132 is capable of comparing, in parallel, non-masked portions of the masked destination address outputted from the corresponding mask circuit 120, 121 or 122 with corresponding portions of each destination address of each table entry stored therein. Finally, the switch memory 100 includes a prioritizer 150 for enabling the output of an output port entry of a matched table entry from the memory array 130, 131 or 132, storing destination addresses of the lowest level in the hierarchy, in which a match occurred.
摘要翻译： 公开了一种用于在交换机中实现多级分层路由表的交换机存储器100。 开关存储器100包括多个屏蔽电路120,121和122，每个屏蔽电路120,121和122分别对应于多层次的一个层级。 每个掩码电路120,121和122接收来话呼叫或分组的目的地址，并且掩蔽与掩蔽电路120,121或122相关联的层级的级别不相对应的接收的目的地址的部分。 提供对应于每个屏蔽电路120,121或122的存储器阵列130,131或132，其能够存储条目表，其中包括输出端口条目和目标地址的多层次层级的一个级别的对应目的地地址 。 此外，每个存储器阵列130,131或132能够并行地比较从相应的屏蔽电路120,121或122输出的被掩蔽的目的地地址的非掩蔽部分与存储的每个表条目的每个目的地地址的对应部分 其中。 最后，切换存储器100包括优先化器150，用于使能从存储器阵列130,131或132输出匹配表条目的输出端口条目，存储发生匹配的层级中的最低级的目标地址 。
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公开(公告)号：US5115436A
公开(公告)日：1992-05-19
申请号：US521114
申请日：1990-05-04
申请人： Anthony J. McAuley
发明人： Anthony J. McAuley
CPC分类号： H03M13/17
摘要： In accordance with an inventive FEC code, data is transmitted in codewords comprising n m-bit symbols. Of the n symbols, k symbols are known information symbols and h symbols are parity symbols for erasure correction. All of the symbols of the codeword are elements of a field of 2.sup.m integers which is closed with respect to addition and multiplication such as a Galois field. To determine the h parity symbols, an encoder circuit derives a matrix corresponding to a set of simultaneous equations in terms of the k known information symbols and the h parity symbols. This set of equations is then solved for the h parity symbols so that a codeword is transmitted comprising k known information symbols and h known parity symbols. At a decoder, the values of up to h erased symbols in the codeword may be reconstructed using a similar set of simultaneous equations.
摘要翻译： 根据本发明的FEC码，在包括n个m位符号的码字中发送数据。 在n个符号中，k个符号是已知的信息符号，h个符号是用于擦除校正的奇偶校验符号。 码字的所有符号是2m个整数的像素的元素，它们相对于诸如伽罗瓦域的加法和相乘来关闭。 为了确定h个奇偶校验符号，编码器电路根据k个已知信息符号和h个奇偶校验符号导出与一组联立方程对应的矩阵。 然后，针对h个奇偶校验符号求解该组方程，从而发送包括k个已知信息符号和h个已知奇偶校验码元的码字。 在解码器中，可以使用相似的一组联立方程来重建码字中的高达h擦除符号的值。
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公开(公告)号：US5930359A
公开(公告)日：1999-07-27
申请号：US717557
申请日：1996-09-23
CPC分类号： G06F17/30982 , G11C15/00
摘要： A system for a pipeline cascaded content addressable memory CAM system for sequentially processing input data includes an input register, a CAM core, cascade logic and an output register. As the memory association functions produce matches in the CAM core, the cascade logic in parallel composites data associated with each matching CAM core. Each cascade processes a separate data input simultaneously then passes on the cumulative results to the next stage.
摘要翻译： 用于顺序处理输入数据的用于管线级联内容可寻址存储器CAM系统的系统包括输入寄存器，CAM内核，级联逻辑和输出寄存器。 由于存储器关联功能在CAM内核中产生匹配，所以级联逻辑并行复合数据与每个匹配的CAM内核相关联。 每个级联同时处理单独的数据输入，然后将累积结果传递到下一个阶段。
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公开(公告)号：US5841874A
公开(公告)日：1998-11-24
申请号：US696453
申请日：1996-08-13
CPC分类号： G06F17/30982 , G11C15/04
摘要： The present invention encompasses a method of storing ternary data that includes the steps of (1) initializing a conversion register by storing binary-to-ternary mask data in a conversion register; (2) storing ternary data in a content addressable memory (CAM) by inputting a single bit binary data to the conversion register, and converting the binary data into two bits of ternary data using the conversion register; and (3) simultaneously storing the two bits of ternary data in first and second memory cells. For subsequent searching, the method further includes the steps of searching for a match of input search binary data to the stored contents of the CAM; providing a match valid output responsive to the input search binary bits matching any of the stored contents; and generating an address corresponding to a location in the CAM where the match is found.
摘要翻译： 本发明包括一种存储三进制数据的方法，包括以下步骤：（1）通过将二进制到三进制掩码数据存储在转换寄存器中来初始化转换寄存器; （2）通过向转换寄存器输入单位二进制数据，并且使用转换寄存器将二进制数据转换成三位数据，将三进制数据存储在内容可寻址存储器（CAM）中; 和（3）在第一和第二存储器单元中同时存储三位数据的两位。 为了后续搜索，该方法还包括以下步骤：搜索输入搜索二进制数据与CAM的存储内容的匹配; 提供响应于匹配任何存储的内容的输入搜索二进制位的匹配有效输出; 并且生成与CAM中找到匹配的位置相对应的地址。
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公开(公告)号：US5526370A
公开(公告)日：1996-06-11
申请号：US222628
申请日：1994-04-04
申请人： Anthony J. McAuley
发明人： Anthony J. McAuley
CPC分类号： H04L1/0057 , H03M13/05
摘要： A new class of error detection codes has powerful error detection properties, as well as significant implementation advantages. The inventive error detection codes are used in communication protocols to protect transmitted data from corruption.
摘要翻译： 一类新的错误检测代码具有强大的错误检测属性以及显着的实现优势。 在通信协议中使用本发明的错误检测码来保护传输的数据不被破坏。
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公开(公告)号：US20120250529A1
公开(公告)日：2012-10-04
申请号：US12788418
申请日：2010-05-27
申请人： John Lee , Subir Das , Anthony J. McAuley
发明人： John Lee , Subir Das , Anthony J. McAuley
CPC分类号： H04W36/005 , H04L45/028 , H04W40/248 , H04W40/38 , H04W84/18 , Y02D70/20
摘要： In a mobile ad-hoc re-routing system in which network nodes are identified by topology dissemination messages, including local “Hello” and global Topographical Control (“TC”) messages, the improvement comprises triggering topology dissemination messages based on at least one of a new neighbor determination and link loss determinations.
摘要翻译： 在移动自组织重路由系统中，其中网络节点由包括本地Hello和全球拓扑结构控制（TC）消息的拓扑传播消息标识，所述改进包括基于新邻居确定中的至少一个来触发拓扑传播消息 和链路损耗确定。
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7.发明授权
公开(公告)号：US5469433A
公开(公告)日：1995-11-21
申请号：US235062
申请日：1994-04-29
申请人： Anthony J. McAuley
发明人： Anthony J. McAuley
CPC分类号： H04L1/1635 , H04L29/06 , H04Q11/0478 , H04L2012/5615 , H04L2012/5652 , H04L69/324
摘要： The present invention is generally directed to the transmission of data in various types of communication systems, including local area networks (LANs) and wide area networks (WANs). A main object of the present invention is to provide a system based on a parallel structure that can assemble and disassemble packet information in constant time, no matter how corrupted, out of order, or duplicated the arriving packets. A further object of the present invention is to provide a system that would improve efficiency in broadband networks, particularly if implemented in a VLSI chip using the low complexity architecture-and-reassembly of the present invention.
摘要翻译： 本发明一般涉及包括局域网（LAN）和广域网（WAN）在内的各种通信系统中的数据传输。 本发明的主要目的是提供一种基于并行结构的系统，其可以不间断地组装和分解分组信息，而不管如何被破坏，无序或复制到达的分组。 本发明的另一个目的是提供一种提高宽带网络效率的系统，特别是如果在使用本发明的低复杂度架构和重新组装的VLSI芯片中实现的。
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