公开(公告)号：US5937285A

公开(公告)日：1999-08-10

申请号：US863109

申请日：1997-05-23

申请人： Jonathan K. Abrokwah ,  Ravi Droopad ,  Corey D. Overgaard ,  Brian Bowers ,  Michael P. LaMacchia ,  Bruce A. Bernhardt

发明人： Jonathan K. Abrokwah ,  Ravi Droopad ,  Corey D. Overgaard ,  Brian Bowers ,  Michael P. LaMacchia ,  Bruce A. Bernhardt

IPC分类号： H01L21/20 ,  H01L21/335 ,  H01L21/8252 ,  H01L29/80

CPC分类号： H01L29/802 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/8252 ,  H01L29/66462

摘要： A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300.degree. C., a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200.degree. C., a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400.degree. C., and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.

摘要翻译： 制造亚微米HFET的方法包括用GaAs的支撑衬底形成缓冲衬底结构，在约300℃的温度下在支撑衬底上生长一部分低温AlGaAs，在该部分生长的低温GaAs层 AlGaAs层，在400℃的温度下在GaAs层上生长的低温AlGaAs层和在第二AlGaAs层上生长的未掺杂的GaAs的缓冲层。 可以在缓冲衬底结构上形成互补的HFET对，因为该结构同样良好地支持p型和n型晶体管的操作。

公开(公告)号：US5930359A

公开(公告)日：1999-07-27

申请号：US717557

申请日：1996-09-23

申请人： Robert Alan Kempke ,  Anthony J. McAuley ,  Michael P. Lamacchia

发明人： Robert Alan Kempke ,  Anthony J. McAuley ,  Michael P. Lamacchia

IPC分类号： G06F17/30 ,  G11C15/00 ,  H04K1/02 ,  H04L1/12 ,  H04L9/00 ,  H04K1/12

CPC分类号： G06F17/30982 ,  G11C15/00

摘要： A system for a pipeline cascaded content addressable memory CAM system for sequentially processing input data includes an input register, a CAM core, cascade logic and an output register. As the memory association functions produce matches in the CAM core, the cascade logic in parallel composites data associated with each matching CAM core. Each cascade processes a separate data input simultaneously then passes on the cumulative results to the next stage.

摘要翻译： 用于顺序处理输入数据的用于管线级联内容可寻址存储器CAM系统的系统包括输入寄存器，CAM内核，级联逻辑和输出寄存器。 由于存储器关联功能在CAM内核中产生匹配，所以级联逻辑并行复合数据与每个匹配的CAM内核相关联。 每个级联同时处理单独的数据输入，然后将累积结果传递到下一个阶段。

公开(公告)号：US5600260A

公开(公告)日：1997-02-04

申请号：US496651

申请日：1995-06-29

申请人： Michael P. LaMacchia ,  William O. Mathes

发明人： Michael P. LaMacchia ,  William O. Mathes

IPC分类号： H03K19/003 ,  H03K19/00

CPC分类号： H03K19/0033 ,  H03K19/00392

摘要： A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

摘要翻译： 用于将电流转向逻辑（CSL）硬化到软错误（通过并扰乱集成电路的逻辑状态的带电粒子）的方法和装置包括硬化的CSL电路或电池（20），其包括三个或更多个电路单元元件 ） 在平行下。 电路单元元件（21）冗余地执行单电池功能。 每个电路单元元件（21）耦合到求和元件（22）内的软误差免疫电阻元件（24和25）。 取决于每个电路单元元件（21）的输入信号（26），电流（23）被引导通过电阻元件（24和25）。 逻辑输出信号（27）不受单个软错误事件的影响，因为总电流（23）的大部分保持转向通过正确的电阻元件（24或25）。

公开(公告)号：US4623846A

公开(公告)日：1986-11-18

申请号：US701727

申请日：1985-02-14

申请人： Michael P. LaMacchia

发明人： Michael P. LaMacchia

IPC分类号： H03K21/10 ,  H03K3/01

CPC分类号： H03K21/10

摘要： A digital clock generator circuit which accepts a rate signal and a master clock signal and generates an output clock signal exhibiting a frequency which is programmed by the rate signal is disclosed. A constant duty cycle characteristic of the output clock signal is obtained regardless of the output clock signal's frequency. A memory element which generates the output signal is placed in one logical state when a counter portion of the present invention reaches a terminal count. The memory element is placed in an opposing logical state whenever the counter achieves 1/2 of its programmed value. A duty cycle compensator makes small timing adjustments to compensate for any truncation error which occurs in dividing the rate signal by two.

摘要翻译： 公开了一种数字时钟发生器电路，其接收速率信号和主时钟信号，并产生表现出由速率信号编程的频率的输出时钟信号。 无论输出时钟信号的频率如何，均可获得输出时钟信号的恒定占空比特性。 当本发明的计数器部分达到终端计数时，产生输出信号的存储元件被置于一个逻辑状态。 每当计数器达到其编程值的1/2时，存储元件被置于相反的逻辑状态。 占空比补偿器进行小的定时调整，以补偿将速率信号除以2时发生的任何截断误差。