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公开(公告)号：US08242850B2
公开(公告)日：2012-08-14
申请号：US12800808
申请日：2010-05-21
摘要： A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives an accumulator increment (i.e., the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to an overflow. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input from a pseudo-random noise generator.
摘要翻译： 具有多模式分频器，数控振荡器和可编程延迟发生器的直接数字频率合成器。 多模式分频器接收具有输入脉冲频率fosc的输入时钟，并且以输入频率的某个整数分数（1 / P）的瞬时频率fVp输出那些脉冲的一些整数。 响应于来自数控振荡器的信号，多模式分配器在至少两个P（1 / P或1 / P + 1）之间选择。 数字控制振荡器在溢出发生之前接收所需的累加器增量（即分割脉冲边缘数），这导致多模式分频器响应于溢出而改变分频比。 数字振荡器还将溢出信号和延迟信号输出到延迟发生器。 延迟信号包含由伪随机噪声发生器的输入引起的相位抖动噪声。
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公开(公告)号：US20100052797A1
公开(公告)日：2010-03-04
申请号：US12229948
申请日：2008-08-28
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , G06F1/025
摘要： A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P(1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fOUT that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.
摘要翻译： 具有多模式分频器，数控振荡器和可编程延迟发生器的直接数字频率合成器。 多模式分频器接收具有输入脉冲频率fosc的输入时钟，并且以输入频率的某个整数分数（1 / P）的瞬时频率fVp输出那些脉冲的一些整数。 响应于来自数控振荡器的信号，多模式分配器在至少两个P（1 / P或1 / P + 1）之间选择。 数字振荡器接收一个值，该值是在溢出发生之前所需的累加器增量（即，分割的脉冲边沿数），这导致多模式分频器响应于接收到溢出信号而改变分频比。 数字振荡器还将溢出信号和延迟信号输出到延迟发生器，该延迟发生器进一步控制多模式分频器输出信号（Vp）的频率以向具有改进的相位的fOUT提供输出信号（VD），并且 相比现有技术的直接数字频率合成器架构的定时抖动性能。
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公开(公告)号：US20130021069A1
公开(公告)日：2013-01-24
申请号：US13562512
申请日：2012-07-31
IPC分类号： H03K21/00
摘要： A direct digital frequency synthesizer includes a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The divider receives an input clock having an input pulse frequency and outputs some integer fraction of those pulses at an instantaneous frequency that is some integer fraction (1/P) of the input frequency. The divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the oscillator. The oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the divider to change divider ratios in response to receiving an overflow signal. The oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator.
摘要翻译： 直接数字频率合成器包括多模除法器，数控振荡器和可编程延迟发生器。 分频器接收具有输入脉冲频率的输入时钟，并以等于输入频率的整数分数（1 / P）的瞬时频率输出那些脉冲的一些整数。 分频器响应于来自振荡器的信号在至少两个P（1 / P或1 / P + 1）之间进行选择。 振荡器接收一个值，该值是在溢出发生之前所需的累加器增量（即，划分的脉冲边沿的数量），这导致分频器响应于接收到溢出信号而改变分频比。 振荡器还向延迟发生器输出溢出信号和延迟信号。 延迟信号包含由从伪随机噪声发生器产生的增量的输入到累加器中的相位抖动噪声。
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公开(公告)号：US20110095830A1
公开(公告)日：2011-04-28
申请号：US12800808
申请日：2010-05-21
IPC分类号： H03L7/00
摘要： A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator. The delay signal further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fOUT that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.
摘要翻译： 具有多模式分频器，数控振荡器和可编程延迟发生器的直接数字频率合成器。 多模式分频器接收具有输入脉冲频率fosc的输入时钟，并且以输入频率的某个整数分数（1 / P）的瞬时频率fVp输出那些脉冲的一些整数。 响应于来自数控振荡器的信号，多模式分配器在至少两个P（1 / P或1 / P + 1）之间选择。 数字振荡器接收一个值，该值是在溢出发生之前所需的累加器增量（即，分割的脉冲边沿的数量），这导致多模式分频器响应于接收到溢出信号而改变分频比。 数字振荡器还将溢出信号和延迟信号输出到延迟发生器。 延迟信号包含由从伪随机噪声发生器产生的增量的输入到累加器中的相位抖动噪声。 延迟信号进一步控制多模式分频器输出信号（Vp）的频率，以提供具有相比于现有技术的直接数字频率合成器架构具有改进的相位和定时抖动性能的fOUT的输出信号（VD）。
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公开(公告)号：US07724097B2
公开(公告)日：2010-05-25
申请号：US12229948
申请日：2008-08-28
CPC分类号： H03L7/0814 , G06F1/025
摘要： A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fout that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.
摘要翻译： 具有多模式分频器，数控振荡器和可编程延迟发生器的直接数字频率合成器。 多模式分频器接收具有输入脉冲频率fosc的输入时钟，并且以输入频率的某个整数分数（1 / P）的瞬时频率fVp输出那些脉冲的一些整数。 响应于来自数控振荡器的信号，多模式分配器在至少两个P（1 / P或1 / P + 1）之间选择。 数字振荡器接收一个值，该值是在溢出发生之前所需的累加器增量（即，分割的脉冲边沿数），这导致多模式分频器响应于接收到溢出信号而改变分频比。 数字振荡器还将溢出信号和延迟信号输出到延迟发生器，该延迟发生器进一步控制多模式分频器输出信号（Vp）的频率，以提供具有改进相位的fout的输出信号（VD），并且 相比现有技术的直接数字频率合成器架构的定时抖动性能。
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