公开(公告)号：US20130003484A1

公开(公告)日：2013-01-03

申请号：US13172592

申请日：2011-06-29

Applicant: Anuj PARASHAR ,  Marc Vernet

Inventor： Anuj PARASHAR ,  Marc Vernet

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C7/18 ,  G11C7/22

Abstract: A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.

Abstract translation: 存储器包括存储器单元，数据线，块选择线和选择电路。 数据线向存储器单元提供数据并从存储器单元提供数据，并且可以将其分组成块。 每个块包括数据线。 每个块选择线与相应的一个块相关联。 选择电路响应于相应的块选择线选择块，并且存储器使用所选择的位线块执行存储器操作。

公开(公告)号：US08526264B2

公开(公告)日：2013-09-03

申请号：US13172592

申请日：2011-06-29

Applicant: Anuj Parashar ,  Marc Vernet

Inventor： Anuj Parashar ,  Marc Vernet

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C7/18 ,  G11C7/22

Abstract: A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.

Abstract translation: 存储器包括存储器单元，数据线，块选择线和选择电路。 数据线向存储器单元提供数据并从存储器单元提供数据，并且可以将其分组成块。 每个块包括数据线。 每个块选择线与相应的一个块相关联。 选择电路响应于相应的块选择线选择块，并且存储器使用所选择的位线块执行存储器操作。