公开(公告)号：US07235994B2

公开(公告)日：2007-06-26

申请号：US10902668

申请日：2004-07-29

申请人： Arnold E. Barish ,  Norman Karl James

发明人： Arnold E. Barish ,  Norman Karl James

IPC分类号： G01R31/26

CPC分类号： G01R31/024

摘要： A mechanism is provided to address a structure under test and to identify a point of failure. A test open line carries a signal that indicates whether a structure under test is open or closed. A test short line carries a signal that indicates whether a structure under test is shorted. A test structure may include an array of cells, where each cell includes a circuit including structures to test. The cells may be scanned using scan only latches and signals on the test open and/or test short lines may be recorded. A test circuit may include a digital mode and an analog mode. The digital mode provides an open or closed value. The analog mode includes a programmable load. The output of the analog mode provides a resistance value that is relative to the programmable load.

摘要翻译： 提供了一种解决被测结构并确定故障点的机制。 测试开路线带有一个信号，指示被测结构是打开还是关闭。 测试短线携带一个信号，指示被测结构是否短路。 测试结构可以包括单元阵列，其中每个单元包括包括要测试的结构的电路。 可以使用仅扫描锁存器扫描单元，并且可以记录测试打开的信号和/或测试短线。 测试电路可以包括数字模式和模拟模式。 数字模式提供打开或关闭的值。 模拟模式包括可编程负载。 模拟模式的输出提供了相对于可编程负载的电阻值。

公开(公告)号：US4967151A

公开(公告)日：1990-10-30

申请号：US420690

申请日：1989-10-11

申请人： Arnold E. Barish ,  David A. Kiesling ,  Mark D. Mayo ,  Walter A. Svarczkopf

发明人： Arnold E. Barish ,  David A. Kiesling ,  Mark D. Mayo ,  Walter A. Svarczkopf

IPC分类号： G01R31/30 ,  G06F11/00

CPC分类号： G06F11/0754 ,  G01R31/3004

摘要： A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors. The third transistor has its first terminal connected to the circuit node, its second terminal connected to the selected resistor, and its control terminal connected to sense the potential at the other of the resistors. The circuit functions to sense the potential difference between the first and second differential output signals. When the potential difference is less than a predetermined level, a second current is sunk through the one resistor so as to lower the potential of the output signal associated with the one resistor relative to the potential of the output signal associated with the other resistor.

摘要翻译： 一种用于测试类型的差分电流开关逻辑电路的电路，包括：偏置电位，连接到偏置电位的两个电阻器，以及响应于输入信号的装置，用于将第一电流吸收通过所选择的一个电阻器，以便产生 电阻器上的第一和第二差分输出信号。 电路包括第一，第二和第三晶体管，每个具有第一和第二端子，用于响应于施加到控制端子的信号传导电流。 提供用于提供电流的装置。 第一晶体管的第一端子连接到电流供应装置，其第二端子连接到电路节点。 第二晶体管的第一端子连接到电路节点，其第二端子连接到偏置电位，并且其控制端子被连接以感测所选择的一个电阻器中的电位。 第三晶体管的第一端子连接到电路节点，其第二端子连接到所选择的电阻器，并且其控制端子连接以感测另一个电阻器上的电位。 电路用于检测第一和第二差分输出信号之间的电位差。 当电位差小于预定电平时，第二电流通过一个电阻器沉没，以便降低与一个电阻器相关联的输出信号相对于与另一个电阻器相关联的输出信号的电位的电位。