公开(公告)号：US4644265A

公开(公告)日：1987-02-17

申请号：US771928

申请日：1985-09-03

申请人： Evan E. Davidson ,  David A. Kiesling

发明人： Evan E. Davidson ,  David A. Kiesling

IPC分类号： H01L21/66 ,  G01R31/28 ,  G01R31/316 ,  G01R31/319 ,  H01L21/822 ,  H01L27/04 ,  G01R15/12

CPC分类号： G01R31/316 ,  G01R31/31924

摘要： Disclosed is a test system having circuitry for reducing off-chip driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit chip. The integrated circuit chip has a plurality of input terminals for receiving an electrical test pattern from the tester. The integrated circuit chip also includes a plurality of output driver circuits having outputs connected to the tester. The test system is characterized in that the integrated circuit chip includes a driver sequencing network under control of the tester for sequentially conditioning the off-chip driver circuits for possible switching.

摘要翻译： 公开了一种具有用于减少片外驱动器切换（ΔI）噪声的电路的测试系统。 测试系统采用连接并电测试集成电路芯片的测试仪。 集成电路芯片具有用于从测试器接收电测试图案的多个输入端子。 集成电路芯片还包括具有连接到测试器的输出的多个输出驱动器电路。 测试系统的特征在于，集成电路芯片包括在测试器的控制下的驱动器排序网络，用于顺序地调节片外驱动电路以进行可能的切换。

公开(公告)号：US4967151A

公开(公告)日：1990-10-30

申请号：US420690

申请日：1989-10-11

申请人： Arnold E. Barish ,  David A. Kiesling ,  Mark D. Mayo ,  Walter A. Svarczkopf

发明人： Arnold E. Barish ,  David A. Kiesling ,  Mark D. Mayo ,  Walter A. Svarczkopf

IPC分类号： G01R31/30 ,  G06F11/00

CPC分类号： G06F11/0754 ,  G01R31/3004

摘要： A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors. The third transistor has its first terminal connected to the circuit node, its second terminal connected to the selected resistor, and its control terminal connected to sense the potential at the other of the resistors. The circuit functions to sense the potential difference between the first and second differential output signals. When the potential difference is less than a predetermined level, a second current is sunk through the one resistor so as to lower the potential of the output signal associated with the one resistor relative to the potential of the output signal associated with the other resistor.

摘要翻译： 一种用于测试类型的差分电流开关逻辑电路的电路，包括：偏置电位，连接到偏置电位的两个电阻器，以及响应于输入信号的装置，用于将第一电流吸收通过所选择的一个电阻器，以便产生 电阻器上的第一和第二差分输出信号。 电路包括第一，第二和第三晶体管，每个具有第一和第二端子，用于响应于施加到控制端子的信号传导电流。 提供用于提供电流的装置。 第一晶体管的第一端子连接到电流供应装置，其第二端子连接到电路节点。 第二晶体管的第一端子连接到电路节点，其第二端子连接到偏置电位，并且其控制端子被连接以感测所选择的一个电阻器中的电位。 第三晶体管的第一端子连接到电路节点，其第二端子连接到所选择的电阻器，并且其控制端子连接以感测另一个电阻器上的电位。 电路用于检测第一和第二差分输出信号之间的电位差。 当电位差小于预定电平时，第二电流通过一个电阻器沉没，以便降低与一个电阻器相关联的输出信号相对于与另一个电阻器相关联的输出信号的电位的电位。

公开(公告)号：US5124591A

公开(公告)日：1992-06-23

申请号：US577353

申请日：1990-09-04

申请人： Francis Chan ,  William M. Chu ,  Edward B. Eichelberger ,  David A. Kiesling

发明人： Francis Chan ,  William M. Chu ,  Edward B. Eichelberger ,  David A. Kiesling

IPC分类号： H03K17/66 ,  G06F13/40 ,  H03K19/013 ,  H03K19/086 ,  H04L25/02

CPC分类号： H04L25/0272 ,  G06F13/4072 ,  H03K19/013 ,  H03K19/086 ,  H04L25/0282

摘要： A low power push pull off chip driver for differential cascode current circuitry is described that includes the collectors of a differential pair directly coupled to bases of a push pull driver and level shifters coupled to the input of the differential pair to prevent saturation of the differential pair.

公开(公告)号：US4553049A

公开(公告)日：1985-11-12

申请号：US540072

申请日：1983-10-07

申请人： Charles W. Cha ,  John W. Hartman ,  David A. Kiesling ,  William J. Scarpero, Jr.

发明人： Charles W. Cha ,  John W. Hartman ,  David A. Kiesling ,  William J. Scarpero, Jr.

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/319 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H03K19/092 ,  H03K17/62

CPC分类号： G01R31/31924 ,  G01R31/31905

摘要： Integrated circuit logic chips often oscillate during testing because the large unbypassed inductance of the test fixture causes off-chip driver switching noise to be fed back to the logic chip power supply. Oscillation may be prevented by adding an inhibit receiver and an off-chip driver inhibit network to the logic chip. The off-chip driver inhibit network provides a fan out path from the inhibit receiver to each off-chip driver. In response to an inhibit signal applied to the inhibit receiver, the inhibit network forces each of the off-chip drivers to the same logical state, the logic state being the natural logic state assumed by the off-chip drivers upon initial application of power to the chip. The driver inhibit receiver and inhibit network are employed to prevent oscillation at chip power-on, during driver and receiver parametric testing and during input test pattern tests.

摘要翻译： 集成电路逻辑芯片在测试期间经常振荡，因为测试夹具的大的非旁路电感导致芯片外驱动器开关噪声反馈到逻辑芯片电源。 可以通过向禁止接收器和片外驱动器禁止网络到逻辑芯片来防止振荡。 片外驱动器禁止网络提供从禁止接收器到每个片外驱动器的扇出路径。 响应于施加到禁止接收器的抑制信号，禁止网络迫使每个片外驱动器处于相同的逻辑状态，逻辑状态是由片外驱动器在初次施加电源时假定的自然逻辑状态 芯片。 在驱动器和接收机参数测试期间以及在输入测试模式测试期间，驱动器禁止接收器和禁止网络用于防止芯片上电时的振荡。