公开(公告)号：US07526593B2

公开(公告)日：2009-04-28

申请号：US11538399

申请日：2006-10-03

申请人： Manas Mandal ,  William P. Tsu ,  Colyn S. Case ,  Ashish Kishen Kaul

发明人： Manas Mandal ,  William P. Tsu ,  Colyn S. Case ,  Ashish Kishen Kaul

IPC分类号： G06F13/36 ,  G06F13/00

CPC分类号： G06F13/404 ,  Y02D10/14 ,  Y02D10/151

摘要： Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.

摘要翻译： 多个数据传输请求可以在诸如PCI Express（PCI-E）总线的分组化总线上合并并发送为单个数据包。 在一个实施例中，如果它们被引导到相同目标设备中的连续地址范围，则组合请求。 有利地使用机会主义合并过程，如果第一请求和后期请求可合并并且在基于总线活动级别动态确定的保留期间内被接收，则将第一请求与稍后的请求合并; 否则，可以在不合并的情况下传送请求。

公开(公告)号：US20080028181A1

公开(公告)日：2008-01-31

申请号：US11689485

申请日：2007-03-21

申请人： Peter C. Tong ,  Sonny S. Yeoh ,  Kevin J. Kranzusch ,  Gary D. Lorensen ,  Kaymann L. Woo ,  Ashish Kishen Kaul ,  Colyn S. Case ,  Stefan A. Gottschalk ,  Dennis K. Ma

发明人： Peter C. Tong ,  Sonny S. Yeoh ,  Kevin J. Kranzusch ,  Gary D. Lorensen ,  Kaymann L. Woo ,  Ashish Kishen Kaul ,  Colyn S. Case ,  Stefan A. Gottschalk ,  Dennis K. Ma

IPC分类号： G06F12/00

CPC分类号： G06F3/14 ,  G06F12/1027 ,  G06F2212/654 ,  G06T1/60 ,  G09G5/36 ,  G09G5/363 ,  G09G2330/026 ,  G09G2360/121 ,  G09G2360/125

摘要： Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.

摘要翻译： 减少或消除系统存储器访问以检索地址转换信息的电路，方法和装置。 在一个示例中，通过用用于将GPU使用的虚拟地址转换为系统存储器使用的物理地址的条目预先填充图形TLB来减少或消除这些访问。 通过锁定或限制显示访问所需的图形TLB中的条目来维护翻译信息。 这可以通过在图形TLB中限制对图形TLB中的某些位置的访问，通过在图形TLB中存储标志或其他识别信息，或通过其他适当的方法来实现。 在另一示例中，内存空间由用于存储基地址和地址范围的GPU的系统BIOS分配。 将地址范围中的虚拟地址添加到基地址中。