公开(公告)号：US09130728B2

公开(公告)日：2015-09-08

申请号：US12485626

申请日：2009-06-16

申请人： Jens Berkmann ,  Axel Huebner

发明人： Jens Berkmann ,  Axel Huebner

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  H04L1/00 ,  H03M13/29 ,  H03M13/39 ,  H03M13/00 ,  G06F12/06

CPC分类号： H04L1/0071 ,  G06F12/0607 ,  H03M13/2903 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/653 ,  H03M13/6566 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation.

摘要翻译： 用于解码级联代码的解码器包括用于使用存储交错操作对接收到的数据进行存储交错的存储输入交织器。 数据存储器耦合到存储输入交织器的输出端，用于存储交错数据的临时存储。 第一存储输出交织器耦合到数据存储器的输出，用于交错从数据存储器读取的数据，并且多个处理器耦合到第一存储输出交织器的输出以访问数据存储器。 此外，用于产生级联代码序列的编码器包括耦合到编码器的输入端的代码交织器，用于施加代码生成交织操作，第一卷积编码器具有耦合到代码交织器的输出的输入端和耦合到存储交织器 涉及用于应用存储交错操作的编码器的输入。

公开(公告)号：US20140068117A1

公开(公告)日：2014-03-06

申请号：US13599926

申请日：2012-08-30

申请人： Axel Huebner ,  Jens Berkmann ,  Michael Janning

发明人： Axel Huebner ,  Jens Berkmann ,  Michael Janning

IPC分类号： G06F3/00

CPC分类号： G06F13/16 ,  G06F13/1673 ,  G06F13/376 ,  G06F13/38 ,  H03M13/2775 ,  H03M13/2957

摘要： A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.

摘要翻译： 提出了诸如turbo解码装置的装置，其中包括地址缓冲装置和元素缓冲装置的中间缓冲装置通信地耦合到多个处理装置和存储装置。 在并行解码处理的周期期间，中间缓冲装置从两个不同的处理装置接收分别对应于存储在存储装置中的代码序列的第一和第二元素的第一和第二地址信息。 在该循环期间，中间缓冲装置基于第一地址信息向存储装置发送对第一元素的请求，并将第二地址信息存储在地址缓冲装置中。 随后，在该周期期间，中间缓冲装置从存储装置接收对应于第一元素的第一元素信息，并将接收到的第一元素信息存储在元素缓存装置中。

公开(公告)号：US20140012399A1

公开(公告)日：2014-01-09

申请号：US13542752

申请日：2012-07-06

申请人： Jens Berkmann ,  Armin Haeutle ,  Axel Huebner

发明人： Jens Berkmann ,  Armin Haeutle ,  Axel Huebner

IPC分类号： G05B13/02

CPC分类号： H04B17/309 ,  H03M13/41 ,  H03M13/63 ,  H04B17/21 ,  H04L1/0061 ,  H04L1/0067 ,  H04W48/16

摘要： A method of detecting a control channel includes receiving data transmitted via a control channel. A path metric and a correction term is computed based on the received data. A decision metric representing a sum or a difference of the path metric and the correction term is computed. Based on the decision metric, it is decided on a detection of the control channel.

摘要翻译： 检测控制信道的方法包括接收通过控制信道发送的数据。 基于所接收的数据来计算路径量度和校正项。 计算表示路径度量和校正项的和或差的决策度量。 基于决策度量，决定对控制信道的检测。

公开(公告)号：US08428538B2

公开(公告)日：2013-04-23

申请号：US12170149

申请日：2008-07-09

申请人： Axel Huebner ,  Reinhard Rueckriem

发明人： Axel Huebner ,  Reinhard Rueckriem

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H04L25/0232 ,  H04B7/0805 ,  H04B17/318 ,  H04L2025/03426

摘要： A radio receiver comprises a processing unit configured to subject a received radio signal to signal switching. A control unit is configured to output a control signal indicative of information related to the signal switching. A channel estimator is coupled to an output of the processing unit and configured to provide channel parameters based on the control signal received from the control unit.

摘要翻译： 无线接收机包括：处理单元，被配置为对所接收的无线电信号进行信号切换。 控制单元被配置为输出指示与信号切换相关的信息的控制信号。 信道估计器耦合到处理单元的输出，并且被配置为基于从控制单元接收的控制信号来提供信道参数。

公开(公告)号：US09128888B2

公开(公告)日：2015-09-08

申请号：US13599926

申请日：2012-08-30

申请人： Axel Huebner ,  Jens Berkmann ,  Michael Janning

发明人： Axel Huebner ,  Jens Berkmann ,  Michael Janning

IPC分类号： G06F13/12 ,  H03M13/00 ,  G06F13/16 ,  G06F13/376 ,  G06F13/38 ,  H03M13/27 ,  H03M13/29

CPC分类号： G06F13/16 ,  G06F13/1673 ,  G06F13/376 ,  G06F13/38 ,  H03M13/2775 ,  H03M13/2957

摘要： A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.

摘要翻译： 提出了诸如turbo解码装置的装置，其中包括地址缓冲装置和元素缓冲装置的中间缓冲装置通信地耦合到多个处理装置和存储装置。 在并行解码处理的周期期间，中间缓冲装置从两个不同的处理装置接收分别对应于存储在存储装置中的代码序列的第一和第二元素的第一和第二地址信息。 在该循环期间，中间缓冲装置基于第一地址信息向存储装置发送对第一元素的请求，并将第二地址信息存储在地址缓冲装置中。 随后，在该周期期间，中间缓冲装置从存储装置接收对应于第一元素的第一元素信息，并将接收到的第一元素信息存储在元素缓存装置中。

公开(公告)号：US08543896B2

公开(公告)日：2013-09-24

申请号：US13022775

申请日：2011-02-08

申请人： Maria Fresia ,  Jens Berkmann ,  Axel Huebner

发明人： Maria Fresia ,  Jens Berkmann ,  Axel Huebner

IPC分类号： H03M13/03

摘要： An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.

公开(公告)号：US20100318755A1

公开(公告)日：2010-12-16

申请号：US12485626

申请日：2009-06-16

申请人： Jens Berkmann ,  Axel Huebner

发明人： Jens Berkmann ,  Axel Huebner

IPC分类号： G06F12/06

CPC分类号： H04L1/0071 ,  G06F12/0607 ,  H03M13/2903 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/653 ,  H03M13/6566 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation.

摘要翻译： 用于解码级联代码的解码器包括用于使用存储交错操作对接收到的数据进行存储交错的存储输入交织器。 数据存储器耦合到存储输入交织器的输出端，用于存储交错数据的临时存储。 第一存储输出交织器耦合到数据存储器的输出，用于交错从数据存储器读取的数据，并且多个处理器耦合到第一存储输出交织器的输出以访问数据存储器。 此外，用于产生级联代码序列的编码器包括耦合到编码器的输入端的代码交织器，用于施加代码生成交织操作，第一卷积编码器具有耦合到代码交织器的输出的输入端和耦合到存储交织器 涉及用于应用存储交错操作的编码器的输入。

公开(公告)号：US20140064413A1

公开(公告)日：2014-03-06

申请号：US13599943

申请日：2012-08-30

申请人： Axel Huebner ,  Jens Berkmann ,  Maria Fresia ,  Armin Hautle

发明人： Axel Huebner ,  Jens Berkmann ,  Maria Fresia ,  Armin Hautle

IPC分类号： H04L27/00

CPC分类号： H03M13/1111 ,  H03M13/2957 ,  H03M13/3715 ,  H03M13/3972 ,  H03M13/6508 ,  H03M13/6516

摘要： A device such as a worker, window-size and iteration control unit (WWICU) is proposed. The WWICU determines processing, iteration, and window information based on format information indicative of one or more formats to be processed by a decoding process. The processing information may include a number of parallel workers, the iteration information may include a number of half-iterations, and the window information may include a window size to be used in the decoding process. The WWICU then determines time information including a total cycle count based on the processing information, the iteration information, and the window information. In response to determining that the total cycle count is not beyond a threshold value, the WWICU may transmit configuration information including the processing, iteration, and window information to a device, such as a turbo decoding device, configurable to perform the decoding process based on the configuration information.

摘要翻译： 提出了诸如工作者，窗口大小和迭代控制单元（WWICU）等设备。 WWICU基于指示要由解码处理处理的一种或多种格式的格式信息来确定处理，迭代和窗口信息。 处理信息可以包括多个并行工作者，迭代信息可以包括多个半迭代，并且窗口信息可以包括要在解码过程中使用的窗口大小。 然后，WWICU基于处理信息，迭代信息和窗口信息来确定包括总周期数的时间信息。 响应于确定总周期计数不超过阈值，WWICU可以将包括处理，迭代和窗口信息的配置信息发送到诸如turbo解码设备的设备，其可配置为基于 配置信息。

公开(公告)号：US20120204081A1

公开(公告)日：2012-08-09

申请号：US13022775

申请日：2011-02-08

申请人： Maria Fresia ,  Jens Berkmann ,  Axel Huebner

发明人： Maria Fresia ,  Jens Berkmann ,  Axel Huebner

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/3972 ,  H03M13/296 ,  H03M13/3723

摘要： An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.

摘要翻译： 用于解码码块的迭代解码器包括被配置为在每个解码迭代中在码块或码子块上执行前向和后向递归的计算单元。 在第一迭代中使用第一前向/后向解码方案，并且在第二次迭代中使用第二前向/后向解码方案。 鉴于前向和后向处理，第一和第二解码方案是不同的。

公开(公告)号：US20100009649A1

公开(公告)日：2010-01-14

申请号：US12170149

申请日：2008-07-09

申请人： Axel Huebner ,  Reinhard Rueckriem

发明人： Axel Huebner ,  Reinhard Rueckriem

IPC分类号： H04B1/16

CPC分类号： H04L25/0232 ,  H04B7/0805 ,  H04B17/318 ,  H04L2025/03426

摘要： A radio receiver comprises a processing unit configured to subject a received radio signal to signal switching. A control unit is configured to output a control signal indicative of information related to the signal switching. A channel estimator is coupled to an output of the processing unit and configured to provide channel parameters based on the control signal received from the control unit.

摘要翻译： 无线接收机包括：处理单元，被配置为对所接收的无线电信号进行信号切换。 控制单元被配置为输出指示与信号切换相关的信息的控制信号。 信道估计器耦合到处理单元的输出，并且被配置为基于从控制单元接收的控制信号来提供信道参数。