公开(公告)号：US3789143A

公开(公告)日：1974-01-29

申请号：US3789143D

申请日：1971-03-29

申请人： BLACKMER D

发明人： BLACKMER D

IPC分类号： H03G1/00 ,  H03G7/06 ,  H04B1/64 ,  H04B3/04

CPC分类号： H04B1/64 ,  H03G1/0005 ,  H03G7/06

摘要： A compander system for audio signal processing, in which two 90* phase separated signals are generated from an input audio signal. Each phase separated signal is processed through a converter which provides an output signal logarithmically related to the instantaneous rms value of the corresponding phase separated signal. The output currents from both converters are proportional to the square of the input currents, hence are summed to yield a virtually ripple free output. This summed output is then scaled and applied to control the gain of a variable gain amplifier which either compresses or expands the original input audio signal according to the gain of the latter amplifier. Thus, the expansion or compression is a continuous linear process proportioned to the rms value of the input audio signal.

摘要翻译： 用于音频信号处理的压缩扩展器系统，其中从输入音频信号生成两个90°相位分离信号。 通过转换器对每个相位分离的信号进行处理，该转换器提供与对应的相位分离信号的瞬时均方根值对数相关的输出信号。 来自两个转换器的输出电流与输入电流的平方成比例，因此相加得到几乎无纹波的输出。 然后对该求和输出进行缩放和应用，以控制可变增益放大器的增益，该增益放大器根据后一放大器的增益来压缩或扩展原始输入音频信号。 因此，扩展或压缩是与输入音频信号的有效值成比例的连续线性处理。

公开(公告)号：US3714462A

公开(公告)日：1973-01-30

申请号：US3714462D

申请日：1971-06-14

申请人： BLACKMER D

发明人： BLACKMER D

IPC分类号： G06G7/163 ,  G06G7/24 ,  H03G1/00 ,  H03G3/04 ,  H03G7/00 ,  G06G7/12

CPC分类号： H03G3/04 ,  G06G7/163 ,  G06G7/24 ,  H03G1/0005 ,  H03G1/0017 ,  H03G7/002

摘要： A gain control or multiplier circuit in which an input operational amplifier has a pair of feedback paths through respective collector-emitter circuits of opposite conductivity type transistors to form a first bipolar circuit for converting an input signal to a log form by virtue of the log-linear transfer characteristics of the transistors. Each transistor of the first circuit has connected to it another transistor for converting the log signal into its antilog. A second operational amplifier is used as an output buffer for the resulting combined output signals from the antilog transistors. One version employs a bias circuit connected between the emitters of the first bipolar circuit transistors to adjust quiescent current. Another version uses a neutralization circuit to pump currents into the input summing junctions of both operational amplifiers to adjust for capacitive storage effects. In all cases, a control voltage is summed with the log signal by applying the voltage to the bases of the log and antilog converting transistors, thereby controlling the gain between the two operational amplifiers.

摘要翻译： 一种增益控制或乘法器电路，其中输入运算放大器具有通过相反导电型晶体管的相应集电极 - 发射极电路的一对反馈路径，以形成第一双极电路，用于通过对数变换将输入信号转换成对数， 晶体管的线性传输特性。 第一电路的每个晶体管已经连接到另一晶体管，用于将对数信号转换成其对数记录。 第二运算放大器用作来自反对数晶体管的所得到的组合输出信号的输出缓冲器。 一个版本采用连接在第一双极电路晶体管的发射极之间的偏置电路来调节静态电流。 另一个版本使用中和电路将电流泵送到两个运算放大器的输入求和结，以调整电容性存储效应。 在所有情况下，通过将电压施加到对数和对数转换晶体管的基极，从而控制两个运算放大器之间的增益，将控制电压与对数信号相加。