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    Explicitly Regioned Memory Organization in a Network Element
    1.
    发明申请
    Explicitly Regioned Memory Organization in a Network Element 失效
    网络元素中明确区域内存组织

    公开(公告)号：US20120173841A1

    公开(公告)日：2012-07-05

    申请号：US12983130

    申请日：2010-12-31

    申请人： Stephan Meier ,  Robert Hathaway ,  Evan Gewirtz ,  Brian Alleyne ,  Edward Ho

    发明人： Stephan Meier ,  Robert Hathaway ,  Evan Gewirtz ,  Brian Alleyne ,  Edward Ho

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F2213/0038 ,  Y02D10/13

    摘要： A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.

    摘要翻译： 包含多种存储器类型和存储器大小的网络元件将逻辑存储器地址转换为物理存储器地址。 接收到具有逻辑存储器地址的数据结构的存储器访问请求，逻辑存储器地址包括标识映射到一个或多个存储器的区域的区域标识符，并且与其值基于处理的一个或多个区域属性的集合相关联 由软件程序员提供的要求和网元的可用存储器。 网元访问对应于区域标识符的区域映射表条目，并且使用与该区域相关联的区域属性来确定该请求的访问目标，确定访问目标内的物理内存地址偏移量，并且生成物理 内存地址。 访问目标包括目标类别的存储器，存储器类内的实例以及存储器类内的实例的特定物理地址空间。 物理存储器地址包括网络路由信息部分，其包括用于将物理存储器地址路由到目标实例的信息，并且包括地址有效载荷部分，其包括用于识别由子目标识别的物理地址空间的信息和物理存储器地址偏移。

    BANK AWARE MULTI-BIT TRIE
    2.
    发明申请
    BANK AWARE MULTI-BIT TRIE 有权
    银行智能多位智能

    公开(公告)号：US20120170580A1

    公开(公告)日：2012-07-05

    申请号：US12983098

    申请日：2010-12-31

    申请人： RAJESH JAGANNATHAN ,  Brian Alleyne ,  Ramanathan Lakshmikanthan

    发明人： RAJESH JAGANNATHAN ,  Brian Alleyne ,  Ramanathan Lakshmikanthan

    IPC分类号： H04L12/56

    CPC分类号： H04L45/54 ,  H04L45/748

    摘要： Embodiments of the invention include a method performed by a bank aware mtrie control module for distributing a plurality of mtrie levels across a plurality of memory banks. The bank aware mtrie control module identifies the plurality of memory banks present and identifies one or more mtrie blocks in one or more mtrie levels, each mtrie block is an array of mtrie nodes associated with an mtrie level. The bank aware mtrie control module stores each mtrie block in one of the plurality of memory banks, all mtrie nodes in a given mtrie block are stored in the same memory bank. For each subsequent mtrie level, the bank aware mtrie control module ensures that each of the mtrie blocks in that mtrie level is stored in one of the plurality of memory banks other than the memory bank storing mtrie blocks of an immediately previous mtrie level.

    摘要翻译： 本发明的实施例包括由银行感知控制模块执行的用于在多个存储体中分配多个层级的方法。 银行感知控制模块识别存在的多个存储器组，并且识别一个或多个层级中的一个或多个存储块，每个mtrie块是与mtrie级相关联的mtrie节点的阵列。 银行认证控制模块将每个mtrie块存储在多个存储体之一中，给定mtrie块中的所有mtrie节点都存储在同一存储体中。 对于每个后续的mtrie级别，银行感知控制模块确保该mtrie级别中的每个mtrie块都存储在多个存储体之一中，而不是存储有紧前一级mtrie级别的存储体的存储体。

    HIERARCHICAL PACKET POLICER
    3.
    发明申请
    HIERARCHICAL PACKET POLICER 有权
    分层分组策略器

    公开(公告)号：US20120170452A1

    公开(公告)日：2012-07-05

    申请号：US13239214

    申请日：2011-09-21

    申请人： Brian Alleyne ,  Sun Den Chen ,  Ramanathan Lakshmikanthan

    发明人： Brian Alleyne ,  Sun Den Chen ,  Ramanathan Lakshmikanthan

    IPC分类号： H04L12/56

    CPC分类号： H04L47/31 ,  H04L47/20 ,  H04L47/215

    摘要： Embodiments of the invention a method for policing a packet at line rate. A hierarchical policer receives a policer request comprising packet characteristics and identifying request configuration information. The hierarchical policer retrieves meter states specified by the request configuration information. The hierarchical policer processes packet characteristics through meters to generate a meter result. The hierarchical policer generates a hierarchical policer table lookup address using a plurality of meter types, a plurality of input color controls, one or more of the packet characteristics, the meter results, and a plurality of coupling algorithm identifiers. The hierarchical policer reads a hierarchical meter result from a hierarchical policer result table, containing at least a final output packet attribute that classifies the packet. The hierarchical policer updates one or more of the meter states based on the plurality of meter state results. The hierarchical policer returns the final packet output to a policing requestor.

    摘要翻译： 本发明的实施例提供了一种以线速度对分组进行管理的方法。 分层策略器接收包含分组特性和识别请求配置信息的策略请求。 分层策略器检索由请求配置信息指定的仪表状态。 分层策略器通过米来处理分组特征，以产生测量结果。 分级策略器使用多个仪表类型，多个输入颜色控制，分组特性中的一个或多个，仪表结果和多个耦合算法标识符来生成分层策略表查找地址。 分层策略器从分层策略器结果表中读取分层计量表结果，其中至少包含对数据包进行分类的最终输出数据包属性。 分层监视器基于多个仪表状态结果来更新仪表状态中的一个或多个。 分层策略器将最终的分组输出返回到管理请求者。

    Hierarchical packet policer
    4.
    发明授权
    Hierarchical packet policer 有权
    层次分组监管器

    公开(公告)号：US08537671B2

    公开(公告)日：2013-09-17

    申请号：US12983111

    申请日：2010-12-31

    申请人： Brian Alleyne ,  Sunden Chen ,  Ramanathan Lakshmikanthan

    发明人： Brian Alleyne ,  Sunden Chen ,  Ramanathan Lakshmikanthan

    IPC分类号： G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

    CPC分类号： H04L47/20 ,  H04L47/215 ,  H04L47/31

    摘要： Embodiments of the invention include a method performed in a packet processor core for policing a packet through a hierarchical policer coupled to one or more policing requestors. The hierarchical policer has a plurality of meter levels including an initial level and one or more subsequent levels. The hierarchical policer creates a meter result at the meter of each meter level using packet characteristics and a meter state for that meter level. The hierarchical policer generates meter level outputs that classify the packet for each meter level and for at least one of the subsequent levels the meter level output is based on the meter level output from a previous meter level. The hierarchical policer performs a meter combine operation that produces a final packet output attribute from the combination of the meter level outputs. The hierarchical policer returns the final packet output attribute to a policing requestor.

    摘要翻译： 本发明的实施例包括在分组处理器核心中执行的方法，用于通过耦合到一个或多个管理请求者的分级策略器来管理分组。 分层监视器具有包括初始级别和一个或多个后续级别的多个仪表级别。 分层监视器使用分组特性和该仪表级的仪表状态在每个仪表级的仪表处创建仪表结果。 分层监视器产生仪表级输出，对每个仪表级进行分组，对于至少一个后续级别，仪表电平输出基于从先前仪表级别输出的仪表电平。 分层监视器执行仪表组合操作，其从仪表级输出的组合产生最终的分组输出属性。 分层策略器将最终的分组输出属性返回给管理请求者。

    Digital counter segmented into short and long access time memory
    7.
    发明授权
    Digital counter segmented into short and long access time memory 有权
    数字计数器分为短和长访问时间存储器

    公开(公告)号：US08700874B2

    公开(公告)日：2014-04-15

    申请号：US12890479

    申请日：2010-09-24

    申请人： Edmund G. Chen ,  Brian Alleyne ,  Robert Hathaway ,  Ranjit J. Rozario ,  Todd D. Basso

    发明人： Edmund G. Chen ,  Brian Alleyne ,  Robert Hathaway ,  Ranjit J. Rozario ,  Todd D. Basso

    IPC分类号： G06F12/00

    CPC分类号： H03K21/38 ,  H03K21/16

    摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.

    摘要翻译： 一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。 发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。 每次主要部件在内存控制器上滚动时，都会确定应该更新次要部件。 此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。 机会更新是基于概率函数和随机数。 辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。 每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

    Hash collision resolution with key compression in a MAC forwarding data structure
    8.
    发明授权
    Hash collision resolution with key compression in a MAC forwarding data structure 有权
    MAC转发数据结构中的密钥压缩的哈希冲突解决方案

    公开(公告)号：US08312066B2

    公开(公告)日：2012-11-13

    申请号：US12957301

    申请日：2010-11-30

    申请人： Rajesh Jagannathan ,  Brian Alleyne ,  Ramanathan Lakshmikanthan

    发明人： Rajesh Jagannathan ,  Brian Alleyne ,  Ramanathan Lakshmikanthan

    IPC分类号： G06F15/173

    CPC分类号： H04L49/3009

    摘要： Embodiments of the invention include a method performed in a media access control (MAC) forwarding control module within a network element for looking up a MAC address and interface (I/F) identifier pair (MAC-I/F pair) from a MAC forwarding data structure that comprises a first tier data structure and a plurality of second tier data structures. The MAC forwarding data structure utilizes compressed keys to index each of the plurality second tier data structures. The compressed key is generated with a desired MAC address and a mask bit list that corresponds with enough bit positions such that all MAC addresses in second tier data structure can be uniquely addressed with just the values of each MAC address in the bit positions listed. As such, the MAC forwarding data structure is constructed so that the total cost of a lookup with the compressed key technique is deterministic and, therefore, O(1).

    摘要翻译： 本发明的实施例包括在网络单元内的媒体访问控制（MAC）转发控制模块中执行的方法，用于从MAC转发查找MAC地址和接口（I / F）标识符对（I / F）标识符对（MAC-I / F对） 包括第一层数据结构和多个第二层数据结构的数据结构。 MAC转发数据结构利用压缩密钥来索引多个第二层数据结构中的每一个。 使用所需的MAC地址和与足够的位位置相对应的掩码位列来生成压缩密钥，使得可以仅仅列出所述位位置中的每个MAC地址的值来唯一地寻址第二层数据结构中的所有MAC地址。 因此，MAC转发数据结构被构造成使得具有压缩密钥技术的查找的总成本是确定性的，并且因此是O（1）。

    Bank aware multi-bit trie
    10.
    发明授权
    Bank aware multi-bit trie 有权
    银行意识多位特里

    公开(公告)号：US08472350B2

    公开(公告)日：2013-06-25

    申请号：US12983098

    申请日：2010-12-31

    申请人： Rajesh Jagannathan ,  Brian Alleyne ,  Ramanathan Lakshmikanthan

    发明人： Rajesh Jagannathan ,  Brian Alleyne ,  Ramanathan Lakshmikanthan

    IPC分类号： H04L12/28

    CPC分类号： H04L45/54 ,  H04L45/748

    摘要： Embodiments of the invention include a method performed by a bank aware mtrie control module for distributing a plurality of mtrie levels across a plurality of memory banks. The bank aware mtrie control module identifies the plurality of memory banks present and identifies one or more mtrie blocks in one or more mtrie levels, each mtrie block is an array of mtrie nodes associated with an mtrie level. The bank aware mtrie control module stores each mtrie block in one of the plurality of memory banks, all mtrie nodes in a given mtrie block are stored in the same memory bank. For each subsequent mtrie level, the bank aware mtrie control module ensures that each of the mtrie blocks in that mtrie level is stored in one of the plurality of memory banks other than the memory bank storing mtrie blocks of an immediately previous mtrie level.

    摘要翻译： 本发明的实施例包括由银行感知控制模块执行的用于在多个存储体中分配多个层级的方法。 银行感知控制模块识别存在的多个存储器组，并且识别一个或多个层级中的一个或多个存储块，每个mtrie块是与mtrie级相关联的mtrie节点的阵列。 银行认证控制模块将每个mtrie块存储在多个存储体之一中，给定mtrie块中的所有mtrie节点都存储在同一存储体中。 对于每个后续的mtrie级别，银行感知控制模块确保该mtrie级别中的每个mtrie块都存储在多个存储体之一中，而不是存储有紧前一级mtrie级别的存储体的存储体。