公开(公告)号：US07818592B2

公开(公告)日：2010-10-19

申请号：US11788215

申请日：2007-04-18

Applicant: Stephan Meier ,  Marius Evers

Inventor： Stephan Meier ,  Marius Evers

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3891 ,  Y02D10/152 ,  Y02D10/171

Abstract: A token-based power control mechanism for an apparatus including a power controller and a plurality of processing devices. The power controller may detect a power budget allotted for the apparatus. The power controller may convert the allotted power budget into a plurality of power tokens, each power token being a portion of the allotted power budget. The power controller may then assign one or more of the plurality of power tokens to each of the processing devices. The assigned power tokens may determine the power allotted for each of the processing devices. The power controller may receive one or more requests from the plurality of processing devices for one or more additional power tokens. In response to receiving the requests, the power controller may determine whether to change the distribution of power tokens among the processing devices.

Abstract translation: 一种用于包括功率控制器和多个处理设备的装置的基于令牌的功率控制机构。 功率控制器可以检测为该装置分配的功率预算。 功率控制器可以将分配的功率预算转换成多个功率令牌，每个功率令牌是分配的功率预算的一部分。 功率控制器然后可以将多个功率令牌中的一个或多个分配给每个处理设备。 分配的功率令牌可以确定为每个处理设备分配的功率。 功率控制器可以从多个处理设备接收一个或多个附加功率令牌的一个或多个请求。 响应于接收到请求，功率控制器可以确定是否改变处理设备之间的功率标记的分布。

公开(公告)号：US20080259960A1

公开(公告)日：2008-10-23

申请号：US12054236

申请日：2008-03-24

Applicant: John G. Favor ,  Edmund G. Chen ,  Stephan Meier

Inventor： John G. Favor ,  Edmund G. Chen ,  Stephan Meier

IPC: H04L29/04

CPC classification number: H04L49/9094 ,  H04L49/90

Abstract: A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets.

Abstract translation: 描述了用于分组的无序处理的方法和装置。 在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。 该方法还包括对于多个重排序上下文中的每一个，分配指示相对于针对该重排序上下文指定的分组的全局顺序的顺序的重排序上下文序列号。 该方法还包括将分组描述符存储在共享重排序缓冲器中的每个分组，以及完成来自全局顺序的至少某些分组的处理。 对于多个重排序上下文中的每一个，该方法还包括为该重排序上下文保留下一个待退休的分组之一的序列号之一的第一指示。 该方法还包括基于序列号从共享重排序缓冲器中退出分组，以相对于多个重排序上下文中的每一个依次排列，但是对于至少某些分组的全局顺序排列。

公开(公告)号：US08402248B2

公开(公告)日：2013-03-19

申请号：US12983130

申请日：2010-12-31

Applicant: Stephan Meier ,  Robert Hathaway ,  Evan Gewirtz ,  Brian Alleyne ,  Edward Ho

Inventor： Stephan Meier ,  Robert Hathaway ,  Evan Gewirtz ,  Brian Alleyne ,  Edward Ho

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2213/0038 ,  Y02D10/13

Abstract: A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.

Abstract translation: 包含多种存储器类型和存储器大小的网络元件将逻辑存储器地址转换为物理存储器地址。 接收到具有逻辑存储器地址的数据结构的存储器访问请求，逻辑存储器地址包括标识映射到一个或多个存储器的区域的区域标识符，并且与其值基于处理的一个或多个区域属性的集合相关联 由软件程序员提供的要求和网元的可用存储器。 网元访问对应于区域标识符的区域映射表条目，并且使用与该区域相关联的区域属性来确定该请求的访问目标，确定访问目标内的物理内存地址偏移量，并且生成物理 内存地址。 访问目标包括目标类别的存储器，存储器类内的实例以及存储器类内的实例的特定物理地址空间。 物理存储器地址包括网络路由信息部分，其包括用于将物理存储器地址路由到目标实例的信息，并且包括地址有效载荷部分，其包括用于识别由子目标识别的物理地址空间的信息和物理存储器地址偏移。

公开(公告)号：US20110276784A1

公开(公告)日：2011-11-10

申请号：US12777087

申请日：2010-05-10

Applicant: Evan Gewirtz ,  Robert Hathaway ,  Stephan Meier ,  Edward Ho

Inventor： Evan Gewirtz ,  Robert Hathaway ,  Stephan Meier ,  Edward Ho

IPC: G06F9/312 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3802

Abstract: In one embodiment, a current candidate thread is selected from each of multiple first groups of threads using a low granularity selection scheme, where each of the first groups includes multiple threads and first groups are mutually exclusive. A second group of threads is formed comprising the current candidate thread selected from each of the first groups of threads. A current winning thread is selected from the second group of threads using a high granularity selection scheme. An instruction is fetched from a memory based on a fetch address for a next instruction of the current winning thread. The instruction is then dispatched to one of the execution units for execution, whereby execution stalls of the execution units are reduced by fetching instructions based on the low granularity and high granularity selection schemes.

Abstract translation: 在一个实施例中，使用低粒度选择方案从多个第一组线程中选择当前候选线程，其中每个第一组包括多个线程，并且第一组是互斥的。 形成第二组线程，包括从第一组线程中选择的当前候选线程。 使用高粒度选择方案从第二组线程中选择当前获胜线程。 基于当前获胜线程的下一条指令的获取地址从存储器中取出指令。 然后将指令分派到一个执行单元进行执行，由此通过基于低粒度和高粒度选择方案获取指令来减少执行单元的执行停顿。

公开(公告)号：US08051227B1

公开(公告)日：2011-11-01

申请号：US12777084

申请日：2010-05-10

Applicant: Evan Gewirtz ,  Robert Hathaway ,  Stephan Meier

Inventor： Evan Gewirtz ,  Robert Hathaway ,  Stephan Meier

IPC: G06F3/00 ,  G06F13/00

CPC classification number: G06F9/544 ,  G06F9/52

Abstract: A command is received from a first agent via a first predetermined memory-mapped register, the first agent being one of multiple agents representing software processes, each being executed by one of processor cores of a network processor in a network element. A first queue associated with the command is identified based on the first predetermined memory-mapped register. A pointer is atomically read from a first hardware-based queue state register associated with the first queue. Data is atomically accessed at a memory location of the memory based on the pointer. The pointer stored in the first hardware-based queue state register is atomically updated, including incrementing the pointer of the first hardware-based queue state register, reading a queue size of the queue from a first hardware-based configuration register associated with the first queue, and wrapping around the pointer if the pointer reaches an end of the first queue based on the queue size.

Abstract translation: 经由第一预定存储器映射寄存器从第一代理接收到命令，第一代理是表示软件进程的多个代理之一，每个由代理网络元件中的网络处理器的处理器核心之一执行。 基于第一预定存储器映射寄存器来识别与命令相关联的第一队列。 从与第一队列相关联的第一基于硬件的队列状态寄存器中原子地读取指针。 基于指针，数据在存储器的存储器位置被原子访问。 存储在第一基于硬件的队列状态寄存器中的指针被原子地更新，包括增加第一基于硬件的队列状态寄存器的指针，从与第一队列相关联的第一基于硬件的配置寄存器读取队列的队列大小 并且如果指针基于队列大小到达第一队列的末尾，则环绕指针。

公开(公告)号：US07349398B1

公开(公告)日：2008-03-25

申请号：US10193504

申请日：2002-07-10

Applicant: John G. Favor ,  Edmund G. Chen ,  Stephan Meier

Inventor： John G. Favor ,  Edmund G. Chen ,  Stephan Meier

IPC: H04L12/56 ,  H04L12/54 ,  G06F9/44

CPC classification number: H04L49/9094 ,  H04L49/90

Abstract: A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets.

Abstract translation: 描述了用于分组的无序处理的方法和装置。 在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。 该方法还包括对于多个重排序上下文中的每一个，分配指示相对于针对该重排序上下文指定的分组的全局顺序的顺序的重排序上下文序列号。 该方法还包括将分组描述符存储在共享重排序缓冲器中的每个分组，以及完成来自全局顺序的至少某些分组的处理。 对于多个重排序上下文中的每一个，该方法还包括为该重排序上下文保留下一个待退休的分组之一的序列号之一的第一指示。 该方法还包括基于序列号从共享重排序缓冲器中重新分组，所述序列号相对于多个重排序上下文中的每一个依次排列，但是对于至少某些分组的全局顺序排除。

公开(公告)号：US20080263373A1

公开(公告)日：2008-10-23

申请号：US11788215

申请日：2007-04-18

Applicant: Stephan Meier ,  Marius Evers

Inventor： Stephan Meier ,  Marius Evers

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3891 ,  Y02D10/152 ,  Y02D10/171

Abstract: A token-based power control mechanism for an apparatus including a power controller and a plurality of processing devices. The power controller may detect a power budget allotted for the apparatus. The power controller may convert the allotted power budget into a plurality of power tokens, each power token being a portion of the allotted power budget. The power controller may then assign one or more of the plurality of power tokens to each of the processing devices. The assigned power tokens may determine the power allotted for each of the processing devices. The power controller may receive one or more requests from the plurality of processing devices for one or more additional power tokens. In response to receiving the requests, the power controller may determine whether to change the distribution of power tokens among the processing devices.

Abstract translation: 一种用于包括功率控制器和多个处理设备的装置的基于令牌的功率控制机构。 功率控制器可以检测为该装置分配的功率预算。 功率控制器可以将分配的功率预算转换成多个功率令牌，每个功率令牌是分配的功率预算的一部分。 功率控制器然后可以将多个功率令牌中的一个或多个分配给每个处理设备。 分配的功率令牌可以确定为每个处理设备分配的功率。 功率控制器可以从多个处理设备接收一个或多个附加功率令牌的一个或多个请求。 响应于接收到请求，功率控制器可以确定是否改变处理设备之间的功率标记的分布。

公开(公告)号：US08656139B2

公开(公告)日：2014-02-18

申请号：US13045919

申请日：2011-03-11

Applicant: Stephan Meier ,  John G. Favor ,  Evan Gewirtz ,  Robert Hathaway ,  Eric Trehus

Inventor： Stephan Meier ,  John G. Favor ,  Evan Gewirtz ,  Robert Hathaway ,  Eric Trehus

IPC: G06F12/00

CPC classification number: G06F9/30043 ,  G06F9/342

Abstract: A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

Abstract translation: 数字处理器将不同大小的指针存储在存储器中。 处理器具体地执行指令来存储长或短指针。 长指针引用存储器逻辑地址空间中的任何地址，而短指针仅引用该空间子集中的任何地址。 然而，短指针的大小比存储在内存中的长度小于长指针。 因此，长指针支持相对较大的地址范围功能，而短指针使用较少的内存。 处理器还执行将长指针或短指针加载到寄存器文件中的指令，并以不需要处理器在执行其他指令时区分不同指针的方式执行指令。 具体来说，处理器将长指针和短指针转换为用于加载到寄存器文件中的通用格式，并将通用格式的指针转换为长或短指针以存储在存储器中。

公开(公告)号：US20120233414A1

公开(公告)日：2012-09-13

申请号：US13045919

申请日：2011-03-11

Applicant: Stephan Meier ,  John G. Favor ,  Evan Gewirtz ,  Robert Hathaway ,  Eric Trehus

Inventor： Stephan Meier ,  John G. Favor ,  Evan Gewirtz ,  Robert Hathaway ,  Eric Trehus

IPC: G06F12/00

CPC classification number: G06F9/30043 ,  G06F9/342

Abstract: A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

Abstract translation: 数字处理器将不同大小的指针存储在存储器中。 处理器具体地执行指令来存储长或短指针。 长指针引用存储器逻辑地址空间中的任何地址，而短指针仅引用该空间子集中的任何地址。 然而，短指针的大小比存储在内存中的长度小于长指针。 因此，长指针支持相对较大的地址范围功能，而短指针使用较少的内存。 处理器还执行将长指针或短指针加载到寄存器文件中的指令，并以不需要处理器在执行其他指令时区分不同指针的方式执行指令。 具体来说，处理器将长指针和短指针转换为用于加载到寄存器文件中的通用格式，并将通用格式的指针转换为长或短指针以存储在存储器中。

公开(公告)号：US20120173841A1

公开(公告)日：2012-07-05

申请号：US12983130

申请日：2010-12-31

Applicant: Stephan Meier ,  Robert Hathaway ,  Evan Gewirtz ,  Brian Alleyne ,  Edward Ho

Inventor： Stephan Meier ,  Robert Hathaway ,  Evan Gewirtz ,  Brian Alleyne ,  Edward Ho

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2213/0038 ,  Y02D10/13

Abstract: A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.

Abstract translation: 包含多种存储器类型和存储器大小的网络元件将逻辑存储器地址转换为物理存储器地址。 接收到具有逻辑存储器地址的数据结构的存储器访问请求，逻辑存储器地址包括标识映射到一个或多个存储器的区域的区域标识符，并且与其值基于处理的一个或多个区域属性的集合相关联 由软件程序员提供的要求和网元的可用存储器。 网元访问对应于区域标识符的区域映射表条目，并且使用与该区域相关联的区域属性来确定该请求的访问目标，确定访问目标内的物理内存地址偏移量，并且生成物理 内存地址。 访问目标包括目标类别的存储器，存储器类内的实例以及存储器类内的实例的特定物理地址空间。 物理存储器地址包括网络路由信息部分，其包括用于将物理存储器地址路由到目标实例的信息，并且包括地址有效载荷部分，其包括用于识别由子目标识别的物理地址空间的信息和物理存储器地址偏移。