公开(公告)号：US08086767B2

公开(公告)日：2011-12-27

申请号：US13102911

申请日：2011-05-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

公开(公告)号：US07962670B2

公开(公告)日：2011-06-14

申请号：US11759031

申请日：2007-06-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G06F3/00 ,  G06F5/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract translation: 耦合到输入/输出引脚的半导体器件包括用于操作第一功能的第一核和用于操作第二功能的第二核。 多路复用器被布置成将输入/输出引脚设置为第一功能或第二功能，并且仲裁器被配置为接收来自核心的使用输入/输出引脚的请求并且将输入/输出引脚的使用 一个核心。 寄存器被布置成在给予第二核心的输入/输出引脚的使用时存储指示延迟的值，由仲裁器施加。

公开(公告)号：US20080304351A1

公开(公告)日：2008-12-11

申请号：US11759031

申请日：2007-06-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G11C8/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract translation: 耦合到输入/输出引脚的半导体器件包括用于操作第一功能的第一核和用于操作第二功能的第二核。 多路复用器被布置成将输入/输出引脚设置为第一功能或第二功能，并且仲裁器被配置为接收来自核心的使用输入/输出引脚的请求并且将输入/输出引脚的使用 一个核心。 寄存器被布置成在给予第二核心的输入/输出引脚的使用时存储指示延迟的值，由仲裁器施加。

公开(公告)号：US20110213903A1

公开(公告)日：2011-09-01

申请号：US13102911

申请日：2011-05-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G06F3/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract translation: 耦合到输入/输出引脚的半导体器件包括用于操作第一功能的第一核和用于操作第二功能的第二核。 多路复用器被布置成将输入/输出引脚设置为第一功能或第二功能，并且仲裁器被配置为接收来自核心的使用输入/输出引脚的请求并且将输入/输出引脚的使用 一个核心。 寄存器被布置成在给予第二核心的输入/输出引脚的使用时存储指示延迟的值，由仲裁器施加。