公开(公告)号：US08560999B2

公开(公告)日：2013-10-15

申请号：US12982570

申请日：2010-12-30

Applicant: Sachin Mathur

Inventor： Sachin Mathur

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation; de-routing the determined net-routing and re-routing the determined net-routing dependent on at least the routing blockage.

Abstract translation: 一种用于设计电子电路的方法，包括确定网络路由中的至少一个保持违规; 插入与每个至少一个保持违例相关联的路由阻塞; 至少路由阻塞取决于确定的网络路由并重新路由确定的网络路由。

公开(公告)号：US08086767B2

公开(公告)日：2011-12-27

申请号：US13102911

申请日：2011-05-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

公开(公告)号：US07613213B2

公开(公告)日：2009-11-03

申请号：US11209230

申请日：2005-08-23

Applicant: Pushkal Yadav ,  Kumar Shakti Singh ,  Chitra Wadhwa ,  Sachin Mathur ,  Ashis Maitra ,  Amandeep Singh Gujral ,  Diljit Singh ,  Yudhishthira Kundu

Inventor： Pushkal Yadav ,  Kumar Shakti Singh ,  Chitra Wadhwa ,  Sachin Mathur ,  Ashis Maitra ,  Amandeep Singh Gujral ,  Diljit Singh ,  Yudhishthira Kundu

IPC: H04J3/02

CPC classification number: H04J3/1611 ,  H04J3/04 ,  H04J3/0685

Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.

Abstract translation: 多个SONET信号的时间复用处理使用相同的共享电路进行成帧，解扰，维护信号处理，控制字节处理和提取，指针跟踪，重定时和报警指示。 这些信号被反序列化并多路复用到一个字节宽的总线上，在共享流水线中处理这些信号。 额外的管道可以扩展到更高容量的SONET信号。 每个流水线都具有与其他流水线进行通信的装置，从而可以在需要时与其他流的处理共享来自一个流的处理的信息。 根据当前优选的实施例，字节在五个时钟周期内通过管线。

公开(公告)号：US07349444B2

公开(公告)日：2008-03-25

申请号：US10924046

申请日：2004-08-23

Applicant: Daniel C. Upp ,  Suvhasis Mukhopadhyay ,  Bart Brosens ,  Kris Van Aken ,  Chitra Wadhwa ,  Sachin Mathur ,  Ramses Valvekens

Inventor： Daniel C. Upp ,  Suvhasis Mukhopadhyay ,  Bart Brosens ,  Kris Van Aken ,  Chitra Wadhwa ,  Sachin Mathur ,  Ramses Valvekens

IPC: H04J3/06

CPC classification number: H04J3/0623

Abstract: Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. According to the presently preferred embodiment, each FIFO is 29 bytes deep. If FIFO depth is 12-17 bytes, no leaking is performed. If the depth is 8-12 bytes or 17-21 bytes, a slow leak rate is set. If the depth is 4-8 bytes or 21-25 bytes, a fast leak rate is set. If the depth is 0-4 bytes or 25-29 bytes, pointer movements are immediate. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received during a sliding window of n×32 seconds (n×256,000 frames).

Abstract translation: 重新定时SONET信号的方法包括从STS-N信号中解复用STS-1信号，缓冲FIFO中的每个STS-1信号，确定随时间的FIFO深度，以及部分地基于FIFO深度确定指针泄漏率， 也基于接收到的指针移动速率。 根据当前优选的实施例，每个FIFO是29字节深。 如果FIFO深度为12-17字节，则不会发生泄漏。 如果深度为8-12字节或17-21字节，则设置缓慢的泄漏率。 如果深度为4-8字节或21-25字节，则设置快速泄漏率。 如果深度为0-4字节或25-29字节，则指针移动立即。 计算的泄漏率基于在nx32秒（nx256,000帧）的滑动窗口期间接收到的指针移动的净数（正和负移动相加的大小）。

公开(公告)号：US20060039415A1

公开(公告)日：2006-02-23

申请号：US10924046

申请日：2004-08-23

Applicant: Daniel Upp ,  Suvhasis Mukhopadhyay ,  Bart Brosens ,  Kris Aken ,  Chitra Wadhwa ,  Sachin Mathur ,  Ramses Valvekens

Inventor： Daniel Upp ,  Suvhasis Mukhopadhyay ,  Bart Brosens ,  Kris Aken ,  Chitra Wadhwa ,  Sachin Mathur ,  Ramses Valvekens

IPC: H04J3/04

CPC classification number: H04J3/0623

Abstract: Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. According to the presently preferred embodiment, each FIFO is 29 bytes deep. If FIFO depth is 12-17 bytes, no leaking is performed. If the depth is 8-12 bytes or 17-21 bytes, a slow leak rate is set. If the depth is 4-8 bytes or 21-25 bytes, a fast leak rate is set. If the depth is 0-4 bytes or 25-29 bytes, pointer movements are immediate. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received during a sliding window of n×32 seconds (n×256,000 frames).

Abstract translation: 重新定时SONET信号的方法包括从STS-N信号中解复用STS-1信号，缓冲FIFO中的每个STS-1信号，确定随时间的FIFO深度，以及部分地基于FIFO深度确定指针泄漏率， 也基于接收到的指针移动速率。 根据当前优选的实施例，每个FIFO是29字节深。 如果FIFO深度为12-17字节，则不会发生泄漏。 如果深度为8-12字节或17-21字节，则设置缓慢的泄漏率。 如果深度为4-8字节或21-25字节，则设置快速泄漏率。 如果深度为0-4字节或25-29字节，则指针移动立即。 计算的泄漏率基于在nx32秒（nx256,000帧）的滑动窗口期间接收到的指针移动的净数（正和负移动相加的大小）。

公开(公告)号：US20110213903A1

公开(公告)日：2011-09-01

申请号：US13102911

申请日：2011-05-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G06F3/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract translation: 耦合到输入/输出引脚的半导体器件包括用于操作第一功能的第一核和用于操作第二功能的第二核。 多路复用器被布置成将输入/输出引脚设置为第一功能或第二功能，并且仲裁器被配置为接收来自核心的使用输入/输出引脚的请求并且将输入/输出引脚的使用 一个核心。 寄存器被布置成在给予第二核心的输入/输出引脚的使用时存储指示延迟的值，由仲裁器施加。

公开(公告)号：US20120174052A1

公开(公告)日：2012-07-05

申请号：US12982570

申请日：2010-12-30

Applicant: Sachin Mathur

Inventor： Sachin Mathur

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation; de-routing the determined net-routing and re-routing the determined net-routing dependent on at least the routing blockage.

Abstract translation: 一种用于设计电子电路的方法，包括确定网络路由中的至少一个保持违规; 插入与每个至少一个保持违例相关联的路由阻塞; 至少路由阻塞取决于确定的网络路由并重新路由确定的网络路由。

公开(公告)号：US07962670B2

公开(公告)日：2011-06-14

申请号：US11759031

申请日：2007-06-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G06F3/00 ,  G06F5/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract translation: 耦合到输入/输出引脚的半导体器件包括用于操作第一功能的第一核和用于操作第二功能的第二核。 多路复用器被布置成将输入/输出引脚设置为第一功能或第二功能，并且仲裁器被配置为接收来自核心的使用输入/输出引脚的请求并且将输入/输出引脚的使用 一个核心。 寄存器被布置成在给予第二核心的输入/输出引脚的使用时存储指示延迟的值，由仲裁器施加。

公开(公告)号：US20060039416A1

公开(公告)日：2006-02-23

申请号：US11209230

申请日：2005-08-23

Applicant: Pushkal Yadav ,  Kumar Singh ,  Chitra Wadhwa ,  Sachin Mathur ,  Ashis Maitra ,  Amandeep Gujral ,  Diljit Singh

Inventor： Pushkal Yadav ,  Kumar Singh ,  Chitra Wadhwa ,  Sachin Mathur ,  Ashis Maitra ,  Amandeep Gujral ,  Diljit Singh

IPC: H04J3/02

CPC classification number: H04J3/1611 ,  H04J3/04 ,  H04J3/0685

Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.

公开(公告)号：US20080304351A1

公开(公告)日：2008-12-11

申请号：US11759031

申请日：2007-06-06

Applicant: Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

Inventor： Alvin Lim ,  Balakrishnan Kangol ,  Sreekumar Padmanabhan ,  Sachin Mathur

IPC: G11C8/00

CPC classification number: G06F13/364 ,  G06F13/4068

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract translation: 耦合到输入/输出引脚的半导体器件包括用于操作第一功能的第一核和用于操作第二功能的第二核。 多路复用器被布置成将输入/输出引脚设置为第一功能或第二功能，并且仲裁器被配置为接收来自核心的使用输入/输出引脚的请求并且将输入/输出引脚的使用 一个核心。 寄存器被布置成在给予第二核心的输入/输出引脚的使用时存储指示延迟的值，由仲裁器施加。