公开(公告)号：US07452804B2

公开(公告)日：2008-11-18

申请号：US11204982

申请日：2005-08-16

申请人： Michael Beck ,  Bee Kim Hong ,  Armin Tilke ,  Hermann Wendt

发明人： Michael Beck ,  Bee Kim Hong ,  Armin Tilke ,  Hermann Wendt

IPC分类号： H01L21/00

CPC分类号： H01L21/76885 ,  Y10S438/926

摘要： In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.

摘要翻译： 在制造半导体器件的方法中，衬垫沉积在晶片的导电区域上，并且模板层沉积在衬垫上。 蚀刻模板层和衬垫以形成用于导电层的模板图案。 第二衬里沉积在模板图案的暴露表面上，并且通过溅射去除第二衬里的暴露的水平表面。 然后将低k电介质层沉积在晶片上，并且通过化学机械抛光将晶片平面化到模板图案。 用湿蚀刻去除模板图案，以在晶片中形成暴露衬垫和第二衬垫的剩余部分的孔。 金属沉积在孔中，晶片的表面通过化学机械抛光进行再生，以产生可沉积的附加金属化层的平面。

公开(公告)号：US08936995B2

公开(公告)日：2015-01-20

申请号：US11365226

申请日：2006-03-01

申请人： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

发明人： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

IPC分类号： H01L21/762 ,  H01L21/77

CPC分类号： H01L29/0649 ,  H01L21/02271 ,  H01L21/76229 ,  H01L21/76232

摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

摘要翻译： 公开了制造半导体器件的隔离区域的方法及其结构。 在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。 所述至少一个沟槽包括侧壁，底面，下部和上部。 第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。 第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。 第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。 第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。 第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。