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28 条记录 (耗时 0.036 秒)

    Methods of fabricating isolation regions of semiconductor devices and structures thereof
    1.
    发明授权
    Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
    制造半导体器件的隔离区域的方法及其结构

    公开(公告)号：US08936995B2

    公开(公告)日：2015-01-20

    申请号：US11365226

    申请日：2006-03-01

    申请人： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

    发明人： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

    IPC分类号： H01L21/762 ,  H01L21/77

    CPC分类号： H01L29/0649 ,  H01L21/02271 ,  H01L21/76229 ,  H01L21/76232

    摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

    摘要翻译： 公开了制造半导体器件的隔离区域的方法及其结构。 在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。 所述至少一个沟槽包括侧壁，底面，下部和上部。 第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。 第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。 第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。 第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。 第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

    Methods of fabricating isolation regions of semiconductor devices and structures thereof
    2.
    发明申请
    Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
    制造半导体器件的隔离区域的方法及其结构

    公开(公告)号：US20070205489A1

    公开(公告)日：2007-09-06

    申请号：US11365226

    申请日：2006-03-01

    申请人： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Hong ,  Roland Hampp

    发明人： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Hong ,  Roland Hampp

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0649 ,  H01L21/02271 ,  H01L21/76229 ,  H01L21/76232

    摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

    摘要翻译： 公开了制造半导体器件的隔离区域的方法及其结构。 在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。 所述至少一个沟槽包括侧壁，底面，下部和上部。 第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。 第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。 第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。 第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。 第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

    Self aligned silicided contacts
    4.
    发明授权
    Self aligned silicided contacts 有权
    自对准硅化物接触

    公开(公告)号：US08159038B2

    公开(公告)日：2012-04-17

    申请号：US12040409

    申请日：2008-02-29

    申请人： Roland Hampp

    发明人： Roland Hampp

    IPC分类号： H01L29/78

    CPC分类号： H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

    摘要翻译： 公开了形成自对准硅化物触点的结构和方法。 该结构包括设置在有源区上的栅电极，设置在栅极上的衬垫和有源区的至少一部分，设置在衬垫上的绝缘层。 第一接触插塞设置在绝缘层和衬垫中，第一接触插头设置在有源区域的一部分上方并与其接触，第一接触插塞包括第一导电材料。 第二接触插塞设置在绝缘层和衬垫中，第二接触插塞设置在栅电极的一部分上方并与其接触，第二接触插塞包括第一导电材料。 接触材料层设置在有源区域中，接触材料层设置在第一接触插塞下方并且包括第一导电材料。

    Methods of forming conductive features and structures thereof
    5.
    发明授权
    Methods of forming conductive features and structures thereof 有权
    形成导电特征的方法及其结构

    公开(公告)号：US07947606B2

    公开(公告)日：2011-05-24

    申请号：US12129479

    申请日：2008-05-29

    申请人： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    发明人： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

    摘要翻译： 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

    Methods of Forming Conductive Features and Structures Thereof
    6.
    发明申请
    Methods of Forming Conductive Features and Structures Thereof 有权
    形成导电特性及结构的方法

    公开(公告)号：US20090294986A1

    公开(公告)日：2009-12-03

    申请号：US12129479

    申请日：2008-05-29

    申请人： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    发明人： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    IPC分类号： H01L23/52 ,  H01L21/4763 ,  H01L21/8238

    CPC分类号： H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

    摘要翻译： 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

    Barrier for Copper Integration in the FEOL
    10.
    发明申请
    Barrier for Copper Integration in the FEOL 审中-公开
    铜在铜焊上的一体化障碍

    公开(公告)号：US20090218692A1

    公开(公告)日：2009-09-03

    申请号：US12040441

    申请日：2008-02-29

    申请人： Roland Hampp

    发明人： Roland Hampp

    IPC分类号： H01L21/768 ,  H01L23/52

    CPC分类号： H01L23/485 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Copper integration in the FEOL stage is disclosed for a preliminary semiconductor device by forming a recess in a substrate of the device, the recess having a bottom surface and sidewall surfaces, depositing a barrier layer having about a 100% step coverage on the sidewall surfaces and the bottom surface, and depositing copper into the recess over the barrier layer to form a contact providing electrical connection to the preliminary semiconductor device.

    摘要翻译： 通过在器件的衬底中形成凹槽，凹部具有底表面和侧壁表面，在侧壁表面上沉积具有约100％阶梯覆盖的阻挡层，并且在侧壁表面上沉积具有约100％阶梯覆盖的势垒层， 底部表面，并且将铜沉积在阻挡层上的凹部中以形成提供与初级半导体器件的电连接的触点。