公开(公告)号：US20060242476A1

公开(公告)日：2006-10-26

申请号：US11103489

申请日：2005-04-12

申请人： Mark Bickerstaff ,  Yi-Chen Li ,  Chris Nicol ,  Bejamin Widdup

发明人： Mark Bickerstaff ,  Yi-Chen Li ,  Chris Nicol ,  Bejamin Widdup

IPC分类号： G11C29/00

CPC分类号： H03M13/2775 ,  H03M13/2714 ,  H03M13/276 ,  H03M13/2771 ,  H03M13/6516 ,  H03M13/6519

摘要： An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.

摘要翻译： 交织器地址发生器具有修剪避免技术。 它预计在IAG计算不正确地址的时间点，并绕过这些事件。 它为所有指定的代码块大小生成一个有效，连续的地址流。 单个地址计算引擎首先在解码器操作的初始H1半迭代期间“违反”生成的地址（对于相关块大小）进行“训练”，然后根据turbo解码器的要求产生连续的正确的地址流。 因此，确定了修剪地址的区域，然后仅在这些区域中执行训练。 因此，修剪事件表的计算和人口在不到传统风格完全训练所需时间的1/10内确定。 生成的修剪事件表被压缩到256位。