公开(公告)号：US11876727B2

公开(公告)日：2024-01-16

申请号：US18110468

申请日：2023-02-16

申请人： Panasonic Holdings Corporation

发明人： Peter Klenner

IPC分类号： H04L47/62 ,  H03M13/27 ,  H04L1/00 ,  H04L47/625

CPC分类号： H04L47/6245 ,  H03M13/27 ,  H03M13/271 ,  H03M13/276 ,  H03M13/2732 ,  H03M13/2785 ,  H03M13/2796 ,  H04L1/0071 ,  H04L1/0076 ,  H04L1/0085 ,  H04L47/6255

摘要： A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

公开(公告)号：US20230418469A1

公开(公告)日：2023-12-28

申请号：US18243809

申请日：2023-09-08

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Kai Chirca ,  Matthew David Pierson ,  David E. Smith ,  Timothy David Anderson

IPC分类号： G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC分类号： G06F3/0604 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/1668 ,  G06F13/4027 ,  G06F12/0855 ,  G06F12/0607 ,  G06F12/0828 ,  G06F12/0831 ,  G06F13/124 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0815 ,  G06F12/0857 ,  G06F13/1663 ,  G06F3/0632 ,  G06F3/0673 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F9/30101 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F13/1642 ,  G06F3/064 ,  G06F9/30123 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/657 ,  G06F2212/304 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1016 ,  G06F12/0846

摘要： Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

公开(公告)号：US11822786B2

公开(公告)日：2023-11-21

申请号：US17590749

申请日：2022-02-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Kai Chirca ,  Timothy David Anderson

IPC分类号： G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0815 ,  G06F13/16 ,  G06F13/40 ,  G06F13/12 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

CPC分类号： G06F3/0604 ,  G06F3/064 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

摘要： Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

公开(公告)号：US09935890B2

公开(公告)日：2018-04-03

申请号：US15092696

申请日：2016-04-07

申请人： Panasonic Corporation

发明人： Peter Klenner

IPC分类号： H04L12/863 ,  H03M13/27 ,  H04L1/00

CPC分类号： H04L47/6245 ,  H03M13/27 ,  H03M13/271 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2785 ,  H03M13/2796 ,  H04L1/0071 ,  H04L1/0076 ,  H04L1/0085 ,  H04L47/6255

摘要： A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a first connection destination of an input terminal of the convolutional interleaver to one end of one of a plurality of branches; a plurality of FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a second connection destination of an output terminal of the convolutional interleaver to the other end of one of the plurality of branches. The first and second switches switch the first and second connection destinations, respectively, when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the first and second connection destinations sequentially and repeatedly among the plurality of branches.

公开(公告)号：US20180049065A1

公开(公告)日：2018-02-15

申请号：US15673013

申请日：2017-08-09

申请人： Electronics and Telecommunications Research Institute

发明人： Chan Ho YOON ,  Young Jo KO

IPC分类号： H04W28/16 ,  H03M13/27 ,  H03M13/00 ,  H04L5/00

CPC分类号： H04W28/16 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/6525 ,  H04J11/005 ,  H04J13/16 ,  H04L5/0001 ,  H04L5/0007 ,  H04L5/0055 ,  H04W72/04

摘要： Disclosed are operation methods of a terminal and a base station in mobile communications. The operation method of the terminal in a mobile communication network, comprises receiving a terminal identifier from a base station; generating a plurality of interleaving parameters based on the terminal identifier; dividing a channel-coded data block into a plurality of sub-blocks, and performing a block interleaving on each of the plurality of sub-blocks using the plurality of interleaving parameters; and transmitting the plurality of sub-blocks on which the block interleaving has been performed, wherein an interleaving pattern of the block interleaving for each of the plurality of sub-blocks is determined by the plurality of interleaving parameters.

公开(公告)号：US20170012737A1

公开(公告)日：2017-01-12

申请号：US15202954

申请日：2016-07-06

申请人： MStar Semiconductor, Inc.

发明人： Chun-Chieh Wang

IPC分类号： H04L1/00 ,  H03M13/27

CPC分类号： H03M13/6552 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/2757 ,  H03M13/276 ,  H03M13/2778 ,  H03M13/2906 ,  H03M13/6561 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0071

摘要： A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.

摘要翻译： 提供了一种对包括多个单元的交错信号执行时间和单元去交织的方法。 该方法包括：提供用于存储单元的第一存储器，每次以一个单元组为单位写入和读取的第一存储器，所述单元组包括K个单元，其中K是大于1的正整数; 提供用于存储从第一存储器读取的单元的第二存储器; 从第一存储器读取单元，并根据多个置换规则的写入规则将单元写入第二存储器，写入到来自相同单元组的第二存储器的K个连续单元; 以及根据所述置换规则的读取规则从所述第二存储器读取所述单元，以使得从所述第二存储器读取的单元完成时间去交织和单元去交织。

公开(公告)号：US09054927B2

公开(公告)日：2015-06-09

申请号：US14531236

申请日：2014-11-03

申请人： Sony Corporation

发明人： Samuel Asanbeng Atungsiri ,  Matthew Paul Athol Taylor ,  John Nicholas Wilson

IPC分类号： H04L27/00 ,  H04L27/26 ,  H04L1/00 ,  H04L5/00

CPC分类号： H04L5/0007 ,  G11C19/00 ,  H03M13/276 ,  H04L1/0071 ,  H04L5/0053 ,  H04L27/14 ,  H04L27/2602 ,  H04L27/2647

摘要： A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

摘要翻译： 数据处理装置将要传送的输入符号映射到正交频分复用（OFDM）符号的预定数量的副载波信号。 数据处理器包括交织器存储器，其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射，读出的顺序与读入不同，顺序是从一组地址确定的，其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。

公开(公告)号：US08874858B2

公开(公告)日：2014-10-28

申请号：US13157085

申请日：2011-06-09

申请人： Nur Engin

发明人： Nur Engin

IPC分类号： H03M13/27 ,  G06F12/00 ,  H03M13/00

CPC分类号： H03M13/2789 ,  H03M13/271 ,  H03M13/2725 ,  H03M13/2739 ,  H03M13/276 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6519 ,  H03M13/6525

摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

摘要翻译： 提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。 可重配置交织器包括多个可重配置计数器。 计数器计数的值的数量可以是其起始值。 交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。 计算元素根据检索到的值计算交织的地址序列。 通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

公开(公告)号：US08601344B1

公开(公告)日：2013-12-03

申请号：US13955862

申请日：2013-07-31

申请人： Hughes Network Systems, LLC

发明人： Rohit Iyer Seshardri ,  Mustafa Eroz ,  Lin-Nan Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2767 ,  H03M13/275 ,  H03M13/276 ,  H03M13/2789

摘要： A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.

公开(公告)号：US20130318416A1

公开(公告)日：2013-11-28

申请号：US13683011

申请日：2012-11-21

申请人： Wen Tong ,  Catherine Leretaille ,  Stephane Gosne

发明人： Wen Tong ,  Catherine Leretaille ,  Stephane Gosne

IPC分类号： H03M13/27

CPC分类号： H03M13/2739 ,  H03M13/00 ,  H03M13/271 ,  H03M13/275 ,  H03M13/276 ,  H03M13/2764 ,  H03M13/2792 ,  H03M13/2957 ,  H03M13/635 ,  H04L1/0041 ,  H04L1/0052 ,  H04L1/0068 ,  H04L1/0071

摘要： A method, an apparatus, and a computer program product for matching a rate of data bits to a desired rate by deletion of redundant data bits or repetition of data bits are disclosed. In a non-interleaved matrix of the data bits, a pattern of bits to be deleted or repeated to provide the desired data rate is determined. An address of each bit in the pattern in a manner inverse to the interleaving process is decoded to produce a respective address of the bit in the matrix. The respective bit in the interleaved data bits is deleted or repeated depending upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits.

摘要翻译： 公开了一种通过删除冗余数据位或重复数据位来将数据比特速率与期望速率相匹配的方法，装置和计算机程序产品。 在数据比特的非交织矩阵中，确定要删除或重复以提供所需数据速率的比特模式。 以与交织处理相反的方式的图案中的每个位的地址被解码以产生矩阵中的位的相应地址。 取决于相应的地址，删除或重复交错数据位中的相应位。 以与用于从数据比特的非交织矩阵产生交错数据比特的地址的编码相同的方式执行地址解码。