公开(公告)号：US20240005968A1

公开(公告)日：2024-01-04

申请号：US17993543

申请日：2022-11-23

Applicant: William Robert Reohr ,  Benjamin Bogan Reohr

Inventor： William Robert Reohr ,  Benjamin Bogan Reohr

IPC: G11C7/10 ,  G11C11/44

CPC classification number: G11C7/1066 ,  G11C7/1063 ,  G11C7/1096 ,  G11C11/44

Abstract: A memory output circuit for selectively propagating proximate memory output data in a memory array of superconducting memory cells includes multiple datum inputs adapted to operably receive corresponding memory state signals from physically adjacent bit lines in the memory array, and at least one logic gate configured to implement logical OR functionality. The logic gate includes multiple inputs, for receiving at least a subset of the datum inputs operatively coupled thereto, and an output for propagating at least one datum output signal. The memory output circuit further includes at least one delay element operatively coupled to a corresponding one of the datum inputs. The delay element is configured to generate an output signal operably connected to a corresponding one of the inputs of the logic gate, the output signal generated by the delay element being a temporal sequence of at least a subset of the memory state signals supplied thereto delayed by a prescribed delay value.