公开(公告)号：US4538243A

公开(公告)日：1985-08-27

申请号：US418526

申请日：1982-09-15

申请人： Bernd Zehner

发明人： Bernd Zehner

IPC分类号： G11C15/04 ,  G11C11/40

CPC分类号： G11C15/04

摘要： An improved memory cell for use in an associative memory has a RAM cell having two output terminals respectively connected to a bit line and a complementary bit line through transistors having respective control electrodes connected to a word line. The outputs of the RAM cell are also cross-connected to the control electrodes of further transistors respectively connected to the bit lines and having a common terminal connected to the controlled electrode of a transistor which determines the state of a hit line. When the word line is activated, information occurring on the bit line is written into the RAM cell. If the word line is non-activated, information supplied by the bit line is compared to information currently stored in the RAM cell and the result of the comparison is utilized to determine the state of the hit line.

摘要翻译： 用于关联存储器的改进的存储单元具有RAM单元，其具有分别通过连接到字线的各个控制电极的晶体管连接到位线和互补位线的两个输出端子。 RAM单元的输出也交叉连接到分别连接到位线的另外的晶体管的控制电极，并且具有连接到确定命中线状态的晶体管的受控电极的公共端子。 当字线被激活时，位线上发生的信息被写入RAM单元。 如果字线未被激活，则由位线提供的信息与当前存储在RAM单元中的信息进行比较，并且利用比较结果来确定命中行的状态。

公开(公告)号：US4864397A

公开(公告)日：1989-09-05

申请号：US173114

申请日：1988-03-24

申请人： Bernd Zehner ,  Fred Matthiesen ,  Matthias Schoebinger ,  Ulrich Totzek

发明人： Bernd Zehner ,  Fred Matthiesen ,  Matthias Schoebinger ,  Ulrich Totzek

IPC分类号： G06T9/00 ,  H04N19/152 ,  H04N19/503 ,  H04N19/593

CPC分类号： H04N19/152 ,  H04N19/503 ,  H04N19/593 ,  H04N19/50

摘要： In a DPCM coder respective estimated values are subtracted from digitized picture element signals and estimated errors are used for signal transmission after quantization and coding. Each estimated value is derived from a reconstructed picture element signal formed in an adder. Separate, simultaneous subtractions of the signal taken at the output of the adder, as well as of the positive and negative adder limit values, from the respective picture element signal at the input thereby occur, whereby an overflow recognition device and a multiplexer provide that only the difference from the three differences formed up to this point are taken into consideration for quantization on the basis of the actual addition result, including no overflow, positive overflow and negative overflow.

摘要翻译： 在DPCM编码器中，从数字化的像素信号中减去相应的估计值，并且将估计的误差用于量化和编码之后的信号传输。 每个估计值从在加法器中形成的重构图像信号导出。 从输入端的各个像素信号中分别同时减去在加法器的输出处获得的信号以及正，负加法器极限值，从而溢出识别装置和多路复用器仅提供 基于实际的相加结果，不包括溢出，正溢出和负溢出，考虑到形成到这一点的三个差的差异进行量化。

公开(公告)号：US4866518A

公开(公告)日：1989-09-12

申请号：US176326

申请日：1988-03-31

申请人： Bernd Zehner ,  Fred Matthiesen ,  Matthias Schoebinger ,  Ulrich Totzek

发明人： Bernd Zehner ,  Fred Matthiesen ,  Matthias Schoebinger ,  Ulrich Totzek

IPC分类号： H04N19/593

CPC分类号： H04N19/593

摘要： In DPCM coders, respective estimated values are subtracted from digitized picture element signals and the estimated errors are employed for signal transmission following quantization and coding. Each estimated error is quantized with a fictitious, positive operational sign in a first programmable logic arrangement and, parallel thereto, is quantized with a fictitious negative operational sign in a second programmable logic arrangement. Of these two quantizing results, the correct result is selected via a multiplexer controlled by the actual operational sign of the estimated error.

摘要翻译： 在DPCM编码器中，从数字化的像素信号中减去相应的估计值，并且将估计的误差用于量化和编码之后的信号传输。 每个估计的误差在第一可编程逻辑布置中用虚构的正的运行符号进行量化，并且与第二可编程逻辑布置中的虚拟负操作符号进行量化。 在这两个量化结果中，通过由估计误差的实际操作符号控制的多路复用器选择正确的结果。

公开(公告)号：US4769778A

公开(公告)日：1988-09-06

申请号：US831791

申请日：1986-02-21

申请人： Reinhard Tielert ,  Bernd Zehner

发明人： Reinhard Tielert ,  Bernd Zehner

IPC分类号： H04N7/26 ,  G11C8/04 ,  G11C11/409 ,  G11C11/4096 ,  H03H17/02 ,  H03H17/06 ,  G06F15/31

CPC分类号： G11C11/4096 ,  G11C11/409 ,  G11C8/04

摘要： A circuit arrangement comprises a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions and contains three-transistor cells having overlapping write/read cycles as storage elements. A row selector is clocked controlled by the input clock of the incoming image signals and is continuously steppable and resettable at any time. The row selector comprises, respectively, two phase offset signal outputs per selection step which respectively drive a write word line and a read word line and which are provided per row of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of the column. A storage amplifier which is disconnectible from the read bit line is provided per column and has an input connected to the read bit line of the assigned column and an output connected to the bit write line of the following column and serves as a data output. A reset input is connected to the setting inputs of a first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time to be set between the undelayed data output and a first, delayed data output. A plurality of such memory-shaped memory arrangements is provided in accordance with the word width of the image data the row selector being provided in common for such plurality, whereby a respective memory block accepts one bit of the image data word and offers the same as the respective corresponding bit of a plurality of differently time delayed output data words. An arithmetic unit combines the data outputs, by adding or, respectively, subtracting, in an arrangement of cascaded logic elements in order to achieve the required filter function.