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公开(公告)号：US4490831A
公开(公告)日：1984-12-25
申请号：US471220
申请日：1983-03-01
CPC分类号： H04B1/69
摘要： A digital pulse detector circuit having a selectable false alarm rate receives an analog input signal containing periodic correlation pulses in a background of noise. The input signal is sampled and digitized to produce a series of digital input samples which are taken for regular time slots within a series of time frames. Each of the digital input samples is summed with a previously stored digital summation sample to produce a new summation digital sample that replaces the summation sample read out of memory to produce the new summation sample. The new digital summation sample is compared to a threshold value to produce a signal confirmed signal to indicate detection of the correlation pulse. When a set number of summation steps are carried out for a particular time slot and the summation value for that time slot has not exceeded the threshold value, that time slot is reset to zero to eliminate accumulated noise. The threshold values of the integrated pulses can be set at the threshold detector to enable the operator to select the false alarm rate.
摘要翻译： 具有可选误报率的数字脉冲检测器电路在噪声背景下接收包含周期性相关脉冲的模拟输入信号。 输入信号被采样和数字化以产生一系列数字输入采样，这些样本在一系列时间帧内用于规则的时隙。 每个数字输入样本与先前存储的数字求和样本相加以产生新的求和数字样本，其取代从存储器读出的求和样本以产生新的求和样本。 将新的数字求和样本与阈值进行比较，以产生信号确认信号，以指示相关脉冲的检测。 当针对特定时隙执行设定数量的求和步骤，并且该时隙的求和值未超过阈值时，该时隙被重置为零以消除累积的噪声。 可以在阈值检测器处设置积分脉冲的阈值，以使操作者能够选择虚警率。
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2.发明授权Method for establishing and maintaining a nodal network in a communication system 失效在通信系统中建立和维护节点网络的方法
公开(公告)号：US4864563A
公开(公告)日：1989-09-05
申请号：US294912
申请日：1989-01-09
IPC分类号： H04L12/56
CPC分类号： H04L45/02 , H04L45/44 , Y10S370/912
摘要： A method for establishing and maintaining a nodal network in a communication system is described using a network connectivity matrix at each node of the network. The network connectivity matrix has a plurality of channels each corresponding to a node of the network and storing nodal information about the connectivity status of the node in the network. Each channel (row) of the network connectivity matrix at each node includes a first field for storing data indicating whether a usable line-of-sight (LOS) transmission path exists between the node and each other node of the network, a second field for storing data indicating when the row was last revised, a third field for storing the identification of the most recent transmission received by the node and a fourth field for storing data indicating a quality of the transmission path between the node and each node within LOS of the node. A method of routing information uses the network connectivity matrix to control distribution of messages throughout the network in a global fashion as well as between specific source and destination nodes.
摘要翻译： 使用在网络的每个节点处的网络连接矩阵来描述在通信系统中建立和维护节点网络的方法。 网络连接矩阵具有多个通道，每个通道对应于网络的节点，并且存储关于网络中的节点的连接状态的节点信息。 每个节点处的网络连接矩阵的每个信道（行）包括用于存储指示在节点和网络的每个其他节点之间是否存在可用的视线（LOS）传输路径的数据的第一字段， 存储指示行最后修改的数据的第三字段，用于存储由节点接收的最近发送的标识的第三字段和用于存储表示节点与节点之间的每个节点之间的传输路径的质量的第四字段 节点。 路由信息的方法使用网络连接矩阵来控制整个网络中的消息的分布，以全局方式以及在特定的源节点和目的节点之间。
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公开(公告)号：US4346480A
公开(公告)日：1982-08-24
申请号：US153551
申请日：1980-05-05
CPC分类号： H03J7/32
摘要： Frequency indication pulses are applied to comparison and feedback logic for the identification of a frequency in a selected frequency band. The comparison and feedback logic is part of an identification circuit that includes a main memory for storing representations of frequency values that is coupled to the comparison and feedback logic by data transfer gating. Control logic coupled to the data transfer gating and main memory provides shift pulses, clock pulses and control signals to sequence the operation of the main memory and comparison and feedback logic. Interval timing and control logic receives from the RF section of the compressive receiver a compare signal, a manual set signal and clock pulses to generate inhibit and enable signals for the comparison and feedback logic, and the control logic. When a comparison in the comparison and feedback logic between a received frequency indication pulse and a memory bit from the main memory indicates the presence of a new frequency, frequency value information, in the form of a sixteen bit data word, is transferred to interface logic and interface memory that encodes a digital word representing a specific frequency occurring within the time constrained subinterval. This digital word representation of a specific frequency is applied to an interface bus as frequency data available to the other sections of the compressive receiver.
摘要翻译： 频率指示脉冲被施加到用于识别所选频带中的频率的比较和反馈逻辑。 比较和反馈逻辑是识别电路的一部分，其包括主存储器，用于存储通过数据传输门控耦合到比较和反馈逻辑的频率值的表示。 耦合到数据传输门控和主存储器的控制逻辑提供移位脉冲，时钟脉冲和控制信号以对主存储器和比较和反馈逻辑的操作进行排序。 间隔定时和控制逻辑从压缩接收机的RF部分接收比较信号，手动设置信号和时钟脉冲，以产生用于比较和反馈逻辑的禁止和使能信号以及控制逻辑。 当来自主存储器的接收频率指示脉冲和存储器位之间的比较和反馈逻辑中的比较指示存在新频率时，以十六位数据字的形式的频率值信息被传送到接口逻辑 以及编码表示在时间受限子区间内发生的特定频率的数字字的接口存储器。 该特定频率的数字字表示作为可用于压缩接收机的其它部分的频率数据应用于接口总线。
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公开(公告)号：US4280218A
公开(公告)日：1981-07-21
申请号：US64845
申请日：1979-08-08
CPC分类号： H04L7/042
摘要： Improved acquisition of signals in a Gaussian noise environment is achieved by applying the output of a correlator (14) to a threshold detector (12). A correlation pulse output from the threshold detector (12) and the output of the correlator (14) are input to a false alarm processor (10) that includes multiple correlation checking channels (22). Each correlation checking channel (22) is assigned to sample an input at various points over a selected interval by an enable pulse generated at the output of select logic (30). Each correlation checking channel (22) includes correlation check enable logic (34), a blanking generator (36), and a confirmation logic (42). In the confirmation logic (42) samples of the analog input are taken at discrete times and integrated over a preselected number of intervals. If this integrated value exceeds a threshold level during the integration interval, the analog input signal is considered valid and a "signal confirmed" pulse is generated and gated through a gate NAND (44) onto a signal confirm line 28.
摘要翻译： 通过将相关器（14）的输出施加到阈值检测器（12）来实现高斯噪声环境中信号的改进获取。 从阈值检测器（12）输出的相关脉冲和相关器（14）的输出被输入到包括多个相关检查通道（22）的假警报处理器（10）。 分配每个相关检查信道（22）以通过在选择逻辑（30）的输出处生成的使能脉冲在所选择的间隔上的各个点对输入进行采样。 每个相关检查信道（22）包括相关检查使能逻辑（34），消隐发生器（36）和确认逻辑（42）。 在确认逻辑（42）中，模拟输入的采样在离散时间被采集，并且以预选的间隔数进行积分。 如果在积分间隔期间该积分值超过阈值电平，则认为模拟输入信号是有效的，并且产生“信号确认”脉冲并通过门NAND（44）选通到信号确认线路28。
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公开(公告)号：US4518947A
公开(公告)日：1985-05-21
申请号：US586996
申请日：1984-03-08
申请人： Billy R. Poston , Carl F. Andren
发明人： Billy R. Poston , Carl F. Andren
摘要： A method and apparatus is disclosed for decoding a redundantly coded digital signal wherein each information character is coded with a plurality of signal elements. Each of the signal elements is sampled by an analog to digital converter (110) and the resulting sample value is transmitted to an adder (114). The sampled value is added to an accumulated sum which is received from a storage circuit (128). The sum of the sampled value and the accumulated sum is transmitted through a selector switch (120) to both a decision circuit (126) and the storage circuit (128). After the last of the redundantly coded signal elements is sampled and the sampled values included within the accumulation sum, the state of the information character is determined by the decision circuit (126). Switch (120) then enters a null data set to reset the accumulated sum to zero for processing the next group of redundantly coded signal elements.
摘要翻译： 公开了一种解码冗余编码数字信号的方法和装置，其中每个信息字符用多个信号元素编码。 每个信号元件由模拟数字转换器（110）采样，并将得到的采样值发送到加法器（114）。 将采样值加到从存储电路（128）接收的累加和。 采样值和累积和之和通过选择器开关（120）发送到判定电路（126）和存储电路（128）。 在冗余编码的信号元素中的最后一个被采样并且包含在累加和之内的采样值之后，由判定电路（126）确定信息字符的状态。 开关（120）然后输入一个空数据集，将累加和复位为零，以处理下一组冗余编码的信号单元。
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