公开(公告)号：US5754875A

公开(公告)日：1998-05-19

申请号：US588694

申请日：1996-01-19

申请人： Klaus Jorg Getzlaff ,  Johann Hajdu ,  Wilhelm Ernst Haller ,  Birgit Withelm

发明人： Klaus Jorg Getzlaff ,  Johann Hajdu ,  Wilhelm Ernst Haller ,  Birgit Withelm

IPC分类号： G06F13/36 ,  G06F9/30 ,  G06F3/14

CPC分类号： G06F9/30112 ,  G06F9/30141

摘要： A computer system is described with a 32 bit arithmetic and logic unit which is coupled to a 64 bit data bus. A number of general purpose registers are provided which have 32 bits each and which are organized in two groups. Two 32 bit data words which are present on the data bus can be transmitted and stored in the two groups of the general purpose registers. From there, the two data words can be transmitted via two operand registers to the arithmetic and logic unit. Several further lines are provided for bypassing the general purpose registers and/or the arithmetic and logic unit, if desired. Due to the fact that two data words can always be transmitted, the performance of the computer system is enhanced.

摘要翻译： 用32位算术和逻辑单元描述计算机系统，该单元耦合到64位数据总线。 提供了多个通用寄存器，每个通用寄存器有32位，并分为两组。 存在于数据总线上的两个32位数据字可以传送并存储在两组通用寄存器中。 从那里，两个数据字可以通过两个操作数寄存器发送到算术和逻辑单元。 如果需要，还提供了几条另外的线路来绕过通用寄存器和/或算术和逻辑单元。 由于可以总是传送两个数据字，因此提高了计算机系统的性能。