公开(公告)号：US5761521A

公开(公告)日：1998-06-02

申请号：US619496

申请日：1996-03-26

申请人： Herbert Chilinski ,  Klaus Joerg Getzlaff ,  Wilhelm Ernst Haller ,  Ralph Koester

发明人： Herbert Chilinski ,  Klaus Joerg Getzlaff ,  Wilhelm Ernst Haller ,  Ralph Koester

IPC分类号： G06F9/305 ,  G06F7/02 ,  G06F9/34 ,  G06F7/00

CPC分类号： G06F7/026

摘要： A processor for character strings A, B of variable length serves for the fast detection of match, mismatch and comparative difference conditions between them. The character strings, whose lengths are delimited by character string termination marks, are split into consecutive substrings with a byte count corresponding to the data path width, and processed to detect a match, a mismatch and an end-of-byte mark. Each substring is routed via operand registers (16,18) in parallel to an arithmetic unit (20), a logic unit (22) and a comparator unit (24) and simultaneously processed. The arithmetic unit (20) subtracts one substring from the other substring, the logic unit (22) compares both substrings with each other and the comparator unit (24) compares the bytes of both substrings with the contents of a marking register (26), previously set to the end-of-string mark. These operations are executed in one machine cycle. Output signals from the comparator unit serve to indicate the equality of both substrings, output signals from the logic unit serve to indicate the inequality of both substrings and a carry signal from the arithmetic unit serves at the same time to indicate which of the two substrings is the greater or the lesser.

摘要翻译： PCT No.PCT / EP94 / 03045 Sec。 371日期：1996年3月26日 102（e）1996年3月26日PCT PCT 1994年9月12日PCT公布。 WO95 / 10803 PCT出版物 日期1995年04月20日可变长度的字符串A，B的处理器用于快速检测它们之间的匹配，不匹配和比较差异条件。 长度由字符串终止符分隔的字符串被分割成与数据路径宽度相对应的字节数的连续子字符串，并被处理以检测匹配，不匹配和字节结尾标记。 每个子串通过操作数寄存器（16,18）并行地运算到运算单元（20），逻辑单元（22）和比较器单元（24）并同时处理。 算术单元（20）从另一个子串中减去一个子串，逻辑单元（22）将两个子串彼此进行比较，比较单元（24）将两个子串的字节与标记寄存器（26）的内容进行比较， 以前设置为字符串结束标记。 这些操作在一个机器周期中执行。 来自比较器单元的输出信号用于指示两个子串的相等，来自逻辑单元的输出信号用于指示两个子串的不等式，并且来自算术单元的进位信号同时工作以指示两个子串中的哪一个是 越来越大。

公开(公告)号：US5754875A

公开(公告)日：1998-05-19

申请号：US588694

申请日：1996-01-19

申请人： Klaus Jorg Getzlaff ,  Johann Hajdu ,  Wilhelm Ernst Haller ,  Birgit Withelm

发明人： Klaus Jorg Getzlaff ,  Johann Hajdu ,  Wilhelm Ernst Haller ,  Birgit Withelm

IPC分类号： G06F13/36 ,  G06F9/30 ,  G06F3/14

CPC分类号： G06F9/30112 ,  G06F9/30141

摘要： A computer system is described with a 32 bit arithmetic and logic unit which is coupled to a 64 bit data bus. A number of general purpose registers are provided which have 32 bits each and which are organized in two groups. Two 32 bit data words which are present on the data bus can be transmitted and stored in the two groups of the general purpose registers. From there, the two data words can be transmitted via two operand registers to the arithmetic and logic unit. Several further lines are provided for bypassing the general purpose registers and/or the arithmetic and logic unit, if desired. Due to the fact that two data words can always be transmitted, the performance of the computer system is enhanced.

摘要翻译： 用32位算术和逻辑单元描述计算机系统，该单元耦合到64位数据总线。 提供了多个通用寄存器，每个通用寄存器有32位，并分为两组。 存在于数据总线上的两个32位数据字可以传送并存储在两组通用寄存器中。 从那里，两个数据字可以通过两个操作数寄存器发送到算术和逻辑单元。 如果需要，还提供了几条另外的线路来绕过通用寄存器和/或算术和逻辑单元。 由于可以总是传送两个数据字，因此提高了计算机系统的性能。