公开(公告)号：US5550503A

公开(公告)日：1996-08-27

申请号：US430999

申请日：1995-04-28

申请人： Doug Garrity ,  David Anderson ,  Howard Anderson ,  Brad Gunter ,  Danny Bersch

发明人： Doug Garrity ,  David Anderson ,  Howard Anderson ,  Brad Gunter ,  Danny Bersch

IPC分类号： G11C27/02 ,  H03K17/06 ,  H03K17/687

CPC分类号： H03K17/6872 ,  G11C27/02 ,  H03K17/063

摘要： A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

摘要翻译： 一种用于当通过传输门（43）对存储电容器（44）充电和放电时减小电压误差的电路和方法。 当禁用传输门（43）时，存储电容器（44）存储或保持通过传输门（43）耦合的电压。 电路包括时钟产生电路（47），其提供用于启用和禁用传输门（43）和电荷反向传输门（46）的互补时钟信号。 时钟发生电路（47）同时向传输门（43,46）提供互补时钟信号。 用于耗散包括传输门（43）的晶体管的通道电荷的替代路径不是通过同时提供互补时钟信号而形成的。 然后，通过充电否定传输门（46）来消除沟道电荷，从而减小存储电容器（44）上的电压误差。