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    System and method for a universal data write unit in a 3-D graphics pipeline including generic cache memories
    1.
    发明申请
    System and method for a universal data write unit in a 3-D graphics pipeline including generic cache memories 有权
    用于包含通用高速缓存存储器的3-D图形管线中的通用数据写入单元的系统和方法

    公开(公告)号：US20050280652A1

    公开(公告)日：2005-12-22

    申请号：US10846774

    申请日：2004-05-14

    申请人： Edward Hutchins ,  Paul Kim ,  Brian Angell

    发明人： Edward Hutchins ,  Paul Kim ,  Brian Angell

    IPC分类号： G06F12/08 ,  G06F13/14 ,  G09G5/36

    CPC分类号： G06F12/0875 ,  G06T1/60 ,  G06T15/005

    摘要： A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.

    摘要翻译： 一种用于包含通用高速缓冲存储器的3-D图形管线中的数据写入单元的系统和方法。 具体地，在一个实施例中，数据写入单元包括第一存储器，多个高速缓冲存储器和数据写入电路。 第一存储器接收与像素相关联的像素分组。 像素分组包括与像素的表面特性有关的数据。 多个高速缓冲存储器耦合到第一存储器，用于存储与多个像素的多个表面特性相关联的像素信息。 多个高速缓冲存储器中的每一个可编程地与指定的表面特性相关联。 数据写入电路耦合到第一个存储器和多个高速缓存存储器。 数据写入电路在程序控制下可操作以获得用于存储到多个高速缓冲存储器中的像素分组的指定部分。

    Interleaving of pixels for low power programmable processor
    2.
    发明申请
    Interleaving of pixels for low power programmable processor 有权
    用于低功率可编程处理器的像素交错

    公开(公告)号：US20050253873A1

    公开(公告)日：2005-11-17

    申请号：US10846334

    申请日：2004-05-14

    申请人： Edward Hutchins ,  Brian Angell

    发明人： Edward Hutchins ,  Brian Angell

    IPC分类号： G09G5/00

    CPC分类号： G06T1/20

    摘要： A graphics processor includes an arithmetic logic unit (ALU) stage for processing pixel packets. Pixels are assigned as either even pixels or odd pixels. The pixel packets of odd and even pixels are interleaved to account for ALU latency.

    摘要翻译： 图形处理器包括用于处理像素数据包的算术逻辑单元（ALU）级。 像素被分配为偶数像素或奇数像素。 奇数和偶数像素的像素包被交织以考虑ALU等待时间。

    Coincident graphics pixel scoreboard tracking system and method
    4.
    发明申请
    Coincident graphics pixel scoreboard tracking system and method 审中-公开
    一致的图形像素记分板跟踪系统和方法

    公开(公告)号：US20060007234A1

    公开(公告)日：2006-01-12

    申请号：US10846208

    申请日：2004-05-14

    申请人： Edward Hutchins ,  Brian Angell ,  Jim Battle ,  Paul Kim

    发明人： Edward Hutchins ,  Brian Angell ,  Jim Battle ,  Paul Kim

    IPC分类号： G06T1/20 ,  G09G5/36

    CPC分类号： G06T15/005

    摘要： Processing pixels in a graphics pipeline. Screen coincidence between a first pixel and a second pixel in a graphics pipeline is detected, wherein the first pixel has entered a downstream pipeline portion of the graphics pipeline but has not yet completed processing within the graphics pipeline. In response to detecting the coincidence, propagation of the second pixel to the downstream pipeline portion is stalled until the first pixel completes processing within the graphics pipeline. A data cache associated with the data fetch stage is invalidated in advance of a data fetch stage of the downstream pipeline portion obtaining data for the second pixel.

    摘要翻译： 处理图形管道中的像素。 检测图形流水线中的第一像素和第二像素之间的屏幕重合，其中第一像素已进入图形流水线的下游流水线部分，但尚未完成图形流水线内的处理。 响应于检测到重合，第二像素到下游流水线部分的传播被停止，直到第一像素在图形流水线内完成处理。 与数据获取级相关联的数据高速缓存在下游流水线部分的数据获取级之前无效，获得第二像素的数据。

    Data format for low power programmable processor
    5.
    发明申请
    Data format for low power programmable processor 有权
    低功耗可编程处理器的数据格式

    公开(公告)号：US20050253862A1

    公开(公告)日：2005-11-17

    申请号：US10846110

    申请日：2004-05-14

    申请人： Edward Hutchins ,  Brian Angell

    发明人： Edward Hutchins ,  Brian Angell

    IPC分类号： G09G5/00

    CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06T1/20

    摘要： A graphics processor includes programmable arithmetic logic units (ALUs) for performing scalar arithmetic operations on pixel packets. For a selected scalar arithmetic operation, operands in pixel packets may be formatted in a S1.8 format to improve dynamic range. For at least one other scalar arithmetic operation, the pixel packets may be formatted in a different data format.

    摘要翻译： 图形处理器包括用于对像素分组执行标量算术运算的可编程算术逻辑单元（ALU）。 对于所选的标量算术运算，像素分组中的操作数可以以S1.8格式格式化，以提高动态范围。 对于至少一个其他标量算术运算，像素分组可以被格式化为不同的数据格式。

    Auto software configurable register address space for low power programmable processor
    6.
    发明申请
    Auto software configurable register address space for low power programmable processor 有权
    自动软件可配置的寄存器地址空间用于低功耗可编程处理器

    公开(公告)号：US20050253856A1

    公开(公告)日：2005-11-17

    申请号：US10846106

    申请日：2004-05-14

    申请人： Edward Hutchins ,  Brian Angell

    发明人： Edward Hutchins ,  Brian Angell

    IPC分类号： G06T1/20 ,  G06T15/00

    CPC分类号： G06T15/005

    摘要： A configurable graphics pipeline has more than one possible process flow of pixel packets through elements of the graphics pipeline. In one embodiment, a data packet triggers an element of the graphics pipeline to discover an identifier.

    摘要翻译： 可配置的图形流水线通过图形流水线的元素具有多个可能的像素数据包流程。 在一个实施例中，数据分组触发图形流水线的元素以发现标识符。

    Statistics instrumentation for low power programmable processor
    7.
    发明申请
    Statistics instrumentation for low power programmable processor 有权
    低功耗可编程处理器统计仪表

    公开(公告)号：US20050253855A1

    公开(公告)日：2005-11-17

    申请号：US10845714

    申请日：2004-05-14

    申请人： Edward Hutchins ,  Brian Angell

    发明人： Edward Hutchins ,  Brian Angell

    IPC分类号： G06T1/20 ,  G06T15/00

    CPC分类号： G06T15/005

    摘要： A graphics processor includes a graphics pipeline having a set of tap points. A configurable test point selector monitors a selected subset of tap points and counts statistics for at least one condition associated with each tap point of the subset of tap points.

    摘要翻译： 图形处理器包括具有一组抽头点的图形管线。 可配置的测试点选择器监视所选择的抽头子集，并对与抽头点子集的每个抽头点相关联的至少一个条件进行统计。

    Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline
    8.
    发明申请
    Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline 有权

    公开(公告)号：US20060268005A1

    公开(公告)日：2006-11-30

    申请号：US11482669

    申请日：2006-07-06

    申请人： Edward Hutchins ,  Brian Angell

    发明人： Edward Hutchins ,  Brian Angell

    IPC分类号： G09G5/00

    CPC分类号： G06T15/005 ,  G06T11/40

    摘要： A rasterizer stage configured to implement multiple interpolators for graphics pipeline. The rasterizer stage includes a plurality of simultaneously operable low precision interpolators for computing a first set of pixel parameters for pixels of a geometric primitive and a plurality of simultaneously operable high precision interpolators for computing a second set of pixel parameters for pixels of the geometric primitive. The rasterizer stage also includes an output mechanism coupled to the interpolators for routing computed pixel parameters into a memory array. Parameters may be programmably assigned to the interpolators and the results thereof may be programmably assigned to portions of a pixel packet.

    Kill bit graphics processing system and method
    10.
    发明申请
    Kill bit graphics processing system and method 有权
    杀死位图形处理系统和方法

    公开(公告)号：US20050280655A1

    公开(公告)日：2005-12-22

    申请号：US10846201

    申请日：2004-05-14

    申请人： Edward Hutchins ,  Brian Angell

    发明人： Edward Hutchins ,  Brian Angell

    IPC分类号： G06T15/00 ,  G09G5/00

    CPC分类号： G06T15/005

    摘要： A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator. The status indicator is a kill bit is set to prevent logic components from clocking information for a payload portion of the pixel packet if the status indicator indicates the pixel packet payload does not contribute to the image display presentation while continuing to clock pixel packet sideband information.

    摘要翻译： 本发明的像素处理系统和方法允许使用包括减少的栅极数量的浅图形管线来呈现复杂的三维图像，并且还有助于功率节省。 像素分组信息包括像素表面属性值在单个统一数据获取阶段检索。 在数据提取管线处，可以确定像素分组信息是否有助于图像显示呈现（例如，执行Z值的深度比较来确定像素是否被遮挡）。 像素分组状态指示符（例如，杀死比特）被设置在像素分组的边带部分中，并且像素分组被转发以根据像素分组状态指示符进行处理。 如果状态指示符指示像素分组有效载荷对图像显示呈现不起作用，同时继续对像素分组边带信息进行时钟处理，则状态指示符是设置为防止逻辑组件针对像素分组的有效载荷部分的时钟信息。