公开(公告)号：US5514979A

公开(公告)日：1996-05-07

申请号：US345307

申请日：1994-11-28

申请人： David F. Collins ,  Brian C. Lacey

发明人： David F. Collins ,  Brian C. Lacey

IPC分类号： H03K5/003 ,  H03K19/003 ,  H03K17/16

CPC分类号： H03K19/00361 ,  H03K5/003

摘要： Disclosed is a bus driver circuit that dynamically clamps the bus voltage for a predetermined period following a transition of the bus voltage, thereby reducing overshoot and ringing. The disclosed circuit dynamically clamps the initial overshoot at approximately the bus terminating voltage VT. The clamping is dynamic in that it is active for only a limited, prescribed period, which is adjustable. In a preferred embodiment, a driver receives an input signal (VIN) and provides an OUTPUT signal to a bus terminated with a terminating voltage (VT). A clamp circuit receives a CLAMP GATE signal and sinks current from the OUTPUT signal, thus reducing ringing and overshoot of the output signal. A delay circuit disables the clamp after a prescribed delay following a transition of the OUTPUT signal.

摘要翻译： 公开了一种总线驱动器电路，其在总线电压转变之后的预定时间段内动态地钳位总线电压，从而减少过冲和振铃。 所公开的电路在大致总线终端电压VT处动态地钳位初始过冲。 夹紧是动态的，因为它仅在有限的规定期间有效，这是可调节的。 在优选实施例中，驱动器接收输入信号（VIN）并且向终止于终止电压（VT）的总线提供OUTPUT信号。 钳位电路接收钳位门信号并从OUTPUT信号吸收电流，从而减少输出信号的振铃和过冲。 延迟电路在OUTPUT信号转换后经过规定的延迟后禁止钳位。

公开(公告)号：US5485107A

公开(公告)日：1996-01-16

申请号：US370115

申请日：1995-01-09

申请人： Brian C. Lacey ,  David F. Collins

发明人： Brian C. Lacey ,  David F. Collins

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018521

摘要： Disclosed is a backplane driver circuit 14' that temporarily clamps its output (PAD) to the termination supply voltage (V.sub.term) during a low to high transition. This termination is applied for a limited period of time determined by the delay through an inverter 14'-15 and a transfer gate 14'-11. This circuit is effective in reducing both the inductive effects of quickly turning the driver off and reflections due to the backplane stubs (L1-L8). Another feature of the driver circuit is that the driver can be plugged into or pulled out of a running system for maintenance without turning the system off. In order to accomplish this, the driver goes into a high impedance state when its supply voltage is turned off.

摘要翻译： 公开了一种背板驱动器电路14'，其在低到高转换期间将其输出（PAD）临时钳位到终端电源电压（Vterm）。 该终止应用在通过逆变器14'-15和传输门14'-11的延迟确定的有限时间段内。 该电路有效地减少了快速关闭驱动器的电感效应和由于背板短路引起的反射（L1-L8）。 驱动器电路的另一个特征是驱动器可以插入或拔出正在运行的系统进行维护，而不会关闭系统。 为了实现这一点，当电源电压关闭时，驱动器进入高阻抗状态。

公开(公告)号：US07170324B2

公开(公告)日：2007-01-30

申请号：US10891048

申请日：2004-07-15

申请人： Carol Ann Huber ,  John C. Kriz ,  Brian C. Lacey ,  Bernard L. Morris

发明人： Carol Ann Huber ,  John C. Kriz ,  Brian C. Lacey ,  Bernard L. Morris

IPC分类号： H03K5/12

CPC分类号： H03K17/163

摘要： A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

摘要翻译： 用于具有可调节转换速率控制的集成电路的缓冲器设计，但与具有压摆率控制的常规缓冲器相比，制造空间要小得多。 将新的压摆率控制电路设计添加到互补金属氧化物半导体CMOS缓冲器中以在缓冲器中实现转换速率控制（例如，在高转换速率和低压摆率之间进行选择）。 新的压摆率控制电路需要明显较少的制造空间，并且当应用于给定集成电路中的每个缓冲器时，例如可以沿着集成电路的外围放置的输入/输出缓冲器，节省的成本是非同寻常的。