公开(公告)号：US06578104B1

公开(公告)日：2003-06-10

申请号：US09345663

申请日：1999-06-30

申请人： Brian D. Small ,  Andrew K. Chan

发明人： Brian D. Small ,  Andrew K. Chan

IPC分类号： G11C1300

CPC分类号： H03K19/1776 ,  G11C7/10 ,  G11C2207/104 ,  G11C2207/108 ,  G11C2207/2254

摘要： A RAM device, such as the type embedded in a programmable logic device, is configurable to alter the depth of the addressable elements and the width of the number of data bits received or produced by the RAM device. The RAM device includes a number of address ports for receiving the read and/or write address signals, but the RAM device may be configured such that the depth requires fewer address signals then there are address ports. Likewise, the RAM device includes a number of input and output data ports for receiving and producing the data bits, but the width of the RAM device may be configured such that the number of data bits actually received or produced are less than the number of data ports. The depth and the width of the RAM device are configured together so that the depth is increased when the width is decreased and vice versa. This permits a number of appropriately configured RAM devices to be combined to produce a deep and wide RAM circuit without requiring the use of additional logic blocks, such as buffers, inverters, and multiplexors that reduce the speed of the circuit.

摘要翻译： 诸如嵌入可编程逻辑器件中的类型的RAM器件可配置为改变可寻址元件的深度以及由RAM器件接收或产生的数据位数的宽度。 RAM设备包括用于接收读取和/或写入地址信号的多个地址端口，但是RAM设备可以被配置为使得深度需要较少的地址信号，然后存在地址端口。 同样地，RAM装置包括用于接收和产生数据位的多个输入和输出数据端口，但是RAM装置的宽度可以被配置为使得实际接收或产生的数据位的数量小于数据的数量 港口。 RAM器件的深度和宽度被配置在一起，使得当宽度减小时深度增加，反之亦然。 这允许多个适当配置的RAM器件组合以产生深而宽的RAM电路，而不需要使用附加逻辑块，例如缓冲器，逆变器和多路复用器，其降低电路的速度。

公开(公告)号：US06519753B1

公开(公告)日：2003-02-11

申请号：US09451681

申请日：1999-11-30

申请人： Roger Ang ,  Atul Ahuja ,  Mukesh T. Lulla ,  Drazen Borkovic ,  Brian D. Small ,  Charles C. Tralka ,  Andrew K. Chan ,  Kevin K. Yee

发明人： Roger Ang ,  Atul Ahuja ,  Mukesh T. Lulla ,  Drazen Borkovic ,  Brian D. Small ,  Charles C. Tralka ,  Andrew K. Chan ,  Kevin K. Yee

IPC分类号： G06F1750

CPC分类号： H03K19/17768 ,  G06F17/5054 ,  H03K19/17732

摘要： A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.

摘要翻译： 诸如现场可编程门阵列的可编程设备包括可由用户编程的主场和被保留用例如由制造商配置的标准电路设计进行编程的至少一个嵌入部分。 嵌入部分类似于主字段，即它具有相同的可编程结构，然而，嵌入部分不能被用户访问。 在一些实施例中，嵌入部分可以用标准电路设计进行预编程，而在其他实施例中，嵌入部分被编程，同时用户编程主字段。 可编程设备还可以包括由编程单元用于将可编程设备识别为具有嵌入部分和哪个标准电路设计编程到嵌入部分中的签名位。 签名位可以在可编程设备的制造之后编程，或者可以在设备的制造期间被硬接线。 编程单元识别签名比特的配置，并基于配置限制对嵌入部分的访问。