公开(公告)号：US06519753B1

公开(公告)日：2003-02-11

申请号：US09451681

申请日：1999-11-30

申请人： Roger Ang ,  Atul Ahuja ,  Mukesh T. Lulla ,  Drazen Borkovic ,  Brian D. Small ,  Charles C. Tralka ,  Andrew K. Chan ,  Kevin K. Yee

发明人： Roger Ang ,  Atul Ahuja ,  Mukesh T. Lulla ,  Drazen Borkovic ,  Brian D. Small ,  Charles C. Tralka ,  Andrew K. Chan ,  Kevin K. Yee

IPC分类号： G06F1750

CPC分类号： H03K19/17768 ,  G06F17/5054 ,  H03K19/17732

摘要： A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.

摘要翻译： 诸如现场可编程门阵列的可编程设备包括可由用户编程的主场和被保留用例如由制造商配置的标准电路设计进行编程的至少一个嵌入部分。 嵌入部分类似于主字段，即它具有相同的可编程结构，然而，嵌入部分不能被用户访问。 在一些实施例中，嵌入部分可以用标准电路设计进行预编程，而在其他实施例中，嵌入部分被编程，同时用户编程主字段。 可编程设备还可以包括由编程单元用于将可编程设备识别为具有嵌入部分和哪个标准电路设计编程到嵌入部分中的签名位。 签名位可以在可编程设备的制造之后编程，或者可以在设备的制造期间被硬接线。 编程单元识别签名比特的配置，并基于配置限制对嵌入部分的访问。

公开(公告)号：US06426649B1

公开(公告)日：2002-07-30

申请号：US09751440

申请日：2000-12-29

申请人： Robert Fu ,  David D. Eaton ,  Kevin K. Yee ,  Andrew K. Chan

发明人： Robert Fu ,  David D. Eaton ,  Kevin K. Yee ,  Andrew K. Chan

IPC分类号： H03K738

CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778 ,  H03L7/183

摘要： A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

摘要翻译： 现场可编程门阵列包括可编程互连结构和多个逻辑单元。 每个逻辑单元包括与可编程互连结构具有直接互连的多个组合逻辑电路，以及用作寄存器的多个顺序逻辑元件，例如D型触发器。 组合逻辑电路可以直接连接到可编程互连结构，并且连接到顺序逻辑元件的输入端。 因此，逻辑单元包括与可编程互连结构的组合和注册连接。 此外，顺序元件之一可以选择性地从可编程互连结构接收专用输入。 逻辑单元的输出引线通过包括保护晶体管的驱动器连接到可编程互连结构。 保护晶体管的栅极耦合到与多个驱动器共享的主电荷泵以及与驱动器相关联的次级电荷泵。

公开(公告)号：US06552410B1

公开(公告)日：2003-04-22

申请号：US09650773

申请日：2000-08-29

申请人： David D. Eaton ,  Ket-Chong Yap ,  Kevin K. Yee ,  E. Thomas Hart ,  Andrew K. Chan ,  Neal A. Palmer ,  Michael W. Dini ,  James Apland ,  Panawalge S. N. Gunaratna

发明人： David D. Eaton ,  Ket-Chong Yap ,  Kevin K. Yee ,  E. Thomas Hart ,  Andrew K. Chan ,  Neal A. Palmer ,  Michael W. Dini ,  James Apland ,  Panawalge S. N. Gunaratna

IPC分类号： H01L2200

CPC分类号： H03K19/1776 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers. The path of the test signal through the JTAG registers is selectable to pass around the periphery of both the programmable and dedicated devices or through the interface and around the periphery of only one of the programmable and dedicated devices.

摘要翻译： 诸如现场可编程门阵列的可编程电路以及诸如ASIC类型器件的专用器件在单个集成电路上与基于反熔丝的接口耦合在一起。 与专用设备通信的可配置非易失性存储器也位于集成电路上。 可编程电路的平台是现有可编程电路的一半，无需设计可编程电路。 可编程电路包括时钟网络，其从时钟端子以及专用器件中的时钟网络接收时钟信号。 专用器件和可编程电路之间的接口包括具有带测试电路的缓冲器的多个导体。 测试电路包括PMOS测试晶体管和NMOS测试晶体管，其允许对缓冲器进行测试而不编程耦合到导体的反熔丝。 使用JTAG寄存器测试周边和可编程电路与专用设备之间的接口中的输入/输出端子。 通过JTAG寄存器的测试信号的路径可选择通过可编程和专用设备的周边，或通过接口和仅可编程和专用设备之一的外围环绕。

公开(公告)号：US06578104B1

公开(公告)日：2003-06-10

申请号：US09345663

申请日：1999-06-30

申请人： Brian D. Small ,  Andrew K. Chan

发明人： Brian D. Small ,  Andrew K. Chan

IPC分类号： G11C1300

CPC分类号： H03K19/1776 ,  G11C7/10 ,  G11C2207/104 ,  G11C2207/108 ,  G11C2207/2254

摘要： A RAM device, such as the type embedded in a programmable logic device, is configurable to alter the depth of the addressable elements and the width of the number of data bits received or produced by the RAM device. The RAM device includes a number of address ports for receiving the read and/or write address signals, but the RAM device may be configured such that the depth requires fewer address signals then there are address ports. Likewise, the RAM device includes a number of input and output data ports for receiving and producing the data bits, but the width of the RAM device may be configured such that the number of data bits actually received or produced are less than the number of data ports. The depth and the width of the RAM device are configured together so that the depth is increased when the width is decreased and vice versa. This permits a number of appropriately configured RAM devices to be combined to produce a deep and wide RAM circuit without requiring the use of additional logic blocks, such as buffers, inverters, and multiplexors that reduce the speed of the circuit.

摘要翻译： 诸如嵌入可编程逻辑器件中的类型的RAM器件可配置为改变可寻址元件的深度以及由RAM器件接收或产生的数据位数的宽度。 RAM设备包括用于接收读取和/或写入地址信号的多个地址端口，但是RAM设备可以被配置为使得深度需要较少的地址信号，然后存在地址端口。 同样地，RAM装置包括用于接收和产生数据位的多个输入和输出数据端口，但是RAM装置的宽度可以被配置为使得实际接收或产生的数据位的数量小于数据的数量 港口。 RAM器件的深度和宽度被配置在一起，使得当宽度减小时深度增加，反之亦然。 这允许多个适当配置的RAM器件组合以产生深而宽的RAM电路，而不需要使用附加逻辑块，例如缓冲器，逆变器和多路复用器，其降低电路的速度。

公开(公告)号：US07346876B2

公开(公告)日：2008-03-18

申请号：US10944323

申请日：2004-09-17

申请人： Andrew K. Chan ,  Thomas M. Chan ,  Po Weng Chiu

发明人： Andrew K. Chan ,  Thomas M. Chan ,  Po Weng Chiu

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F11/00 ,  H03K19/173 ,  H01L25/00

CPC分类号： G09G5/363 ,  G09G2310/0229 ,  G09G2320/106 ,  G09G2340/0407 ,  H04N5/21 ,  H04N5/4401 ,  H04N5/46

摘要： A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function. I/O terminals that were used to couple to the external FPGA during system development are usable during normal operation to provide system board access to circuitry within the mask-programmable portion.

摘要翻译： 公开了一种方法，其中提供了用于不同制造的大容量电子消费装置的便宜的集成电路，其中每个不同的制品必须执行不同的特殊功能。 在所有不同的构成中所需的共同功能在基本不可定制的部分中实现。 提供密集的可编程部分，用于实现特殊功能。 提供了接口电路，使得外部FPGA能够在系统开发过程中以系统运行速度执行特殊功能。 系统开发后，外部FPGA中实现的电路技术映射到掩模可编程部分。 形成单个掩模，使得集成电路的版本通过其定制的掩模可编程部分产生以执行特殊功能。 用于在系统开发过程中耦合到外部FPGA的I / O端子在正常操作期间可用，以提供系统板访问掩模可编程部分内的电路。

公开(公告)号：US06101074A

公开(公告)日：2000-08-08

申请号：US94462

申请日：1998-06-10

申请人： James M. Apland ,  Andrew K. Chan

发明人： James M. Apland ,  Andrew K. Chan

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K17/223 ,  H03K19/17772 ,  H03K19/17784

摘要： A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

摘要翻译： 保护电路在门阵列加电期间防止现场可编程门阵列中的逻辑模块中的电流尖峰。 保护电路在上电期间将电压提供给逻辑模块的内部禁止输入，直到由电荷泵输出的电压达到预定电压。 内部禁用输入端的电压关闭逻辑模块中的晶体管，并防止电流尖峰。 当电荷泵输出的电压达到预定电压时，保护电路不再将电压提供给逻辑模块的内部禁止输入。

公开(公告)号：US5726586A

公开(公告)日：1998-03-10

申请号：US744225

申请日：1996-11-05

申请人： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

发明人： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC分类号： H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

摘要： A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

公开(公告)号：US5416367A

公开(公告)日：1995-05-16

申请号：US189352

申请日：1994-01-31

申请人： Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua ,  William D. Cox

发明人： Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua ,  William D. Cox

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

摘要翻译： 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的多个逻辑单元（“模块”）。 每个逻辑单元都是一个功能强大的通用逻辑构建块。 每个逻辑单元基本上由四个双输入与门，一个或两个六输入与门，三个多路复用器和D型触发器组成。

公开(公告)号：US5220213A

公开(公告)日：1993-06-15

申请号：US847137

申请日：1992-03-06

申请人： Andrew K. Chan ,  Hua-Thye Chua

发明人： Andrew K. Chan ,  Hua-Thye Chua

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

摘要： A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

摘要翻译： 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种功能强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US07830449B2

公开(公告)日：2010-11-09

申请号：US11732434

申请日：2007-04-03

申请人： Qinggang Zhou ,  Clyde H. Nagakura ,  Sheng-Fu Wu ,  Andrew K. Chan

发明人： Qinggang Zhou ,  Clyde H. Nagakura ,  Sheng-Fu Wu ,  Andrew K. Chan

IPC分类号： H04N7/01 ,  H04N11/02

CPC分类号： H04N7/0135 ,  G06T3/4023 ,  G09G5/363 ,  G09G2310/0229 ,  G09G2320/106 ,  G09G2340/0407 ,  H04N5/21 ,  H04N7/012

摘要： A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

摘要翻译： 显示处理器集成电路包括显示处理器部分和片上可编程逻辑部分。 可编程逻辑部分可被配置为实现定制的视频和/或图像增强功能。 显示处理器部分执行基于块的运动检测。 如果对于给定的像素块没有检测到运动，则使用时间插值来填充块中的行间隙。 如果检测到运动，则使用空间插值填充行间隙。 为了保持精度而不会不适当地增加计算复杂度，在不检测到低角度倾斜条件的情况下采用较不复杂的高角度空间插值方法。 因此，在低角度倾斜条件下可以采用更计算密集的低角度空间插值方法。 在读取其他部分的同时进行插值处理的同时，通过采用流水线来编写段缓冲器的部分来减少集成电路成本。