公开(公告)号：US4544851A

公开(公告)日：1985-10-01

申请号：US298035

申请日：1981-08-31

申请人： Marvin Conrad ,  Karl M. Guttag ,  John V. Schabowski ,  Derek Roskell ,  Jim A. Carey ,  Brian Shore

发明人： Marvin Conrad ,  Karl M. Guttag ,  John V. Schabowski ,  Derek Roskell ,  Jim A. Carey ,  Brian Shore

IPC分类号： G06F1/12 ,  H03K3/037 ,  H03K17/30 ,  H03K17/693 ,  H03K19/096

CPC分类号： G06F1/12 ,  H03K3/037 ,  H03K3/0375

摘要： A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of input signal. This circuitry is connected to the remainder of the digital synchronizer which includes a latch connected to the level input and a level sensitive circuit connected to the output of the latch. The latch is constructed to provide a rapid transition between a logic "0" and "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from a logic "0" to a logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for a three quarter of a machine cycle to allow any transient conditions within the latch to dampen out.

摘要翻译： 一种数字同步器电路，包括用于接收异步电平的输入端和用于接收同步脉冲的第二输入端。 两个输入都连接到同步器输入电路，该输入电路将为任一类型的输入信号提供电平输出。 该电路连接到数字同步器的其余部分，其包括连接到电平输入的锁存器和连接到锁存器的输出的电平敏感电路。 锁存器被构造成在逻辑“0”和“1”之间提供快速转换。 此外，锁存器周期性地清零。 电平敏感电路为可能存在于锁存器中的任何亚稳态提供传播屏障。 然而，电平敏感电路也被构造成当在锁存器内发生这种状态时从逻辑“0”到逻辑“1”的快速转变。 在另一实施例中连接另外的闩锁以提供同步器电路的附加可靠性。 第二个锁存器是两个逆变器锁存器，刷新时间为机器周期的四分之一，以允许锁存器内的任何瞬态条件被抑制。

公开(公告)号：US4532587A

公开(公告)日：1985-07-30

申请号：US296283

申请日：1981-08-26

申请人： Derek Roskell ,  John V. Schabowski ,  Karl M. Guttag ,  Kevin C. McDonough ,  Brian Shore ,  Thomas Preston

发明人： Derek Roskell ,  John V. Schabowski ,  Karl M. Guttag ,  Kevin C. McDonough ,  Brian Shore ,  Thomas Preston

IPC分类号： G06F15/78 ,  G06F13/00

CPC分类号： G06F15/7864

摘要： A digital processing system includes an external memory for the storage of program instructions for use with a separate processor that internally contains a memory for temporary storage, an arithmetic and logic means, a register set, control and timing circuitry, and two sets of data paths. The first set of data paths provide access to the external memory for transfer of instructions from the external memory to the processing unit. The second set of data paths provide for the internal routing of instructions data and addresses within the processor unit itself. The data structure for the first set of data paths is different than that for the second set of data paths, providing for an external data structure that is different than the internal data structure of the processor.

摘要翻译： 数字处理系统包括用于存储用于内部包含用于临时存储的存储器的单独处理器的程序指令的外部存储器，算术和逻辑装置，寄存器组，控制和定时电路以及两组数据路径 。 第一组数据路径提供对外部存储器的访问，用于将指令从外部存储器传送到处理单元。 第二组数据路径提供处理器单元本身内的指令数据和地址的内部路由。 用于第一组数据路径的数据结构与第二组数据路径的数据结构不同，提供与处理器的内部数据结构不同的外部数据结构。