公开(公告)号：US06505260B2

公开(公告)日：2003-01-07

申请号：US09784690

申请日：2001-02-15

申请人： Kenneth T. Chin ,  C. Kevin Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jeffrey C. Stevens

发明人： Kenneth T. Chin ,  C. Kevin Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jeffrey C. Stevens

IPC分类号： G06F1318

CPC分类号： G06F13/1605

摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

摘要翻译： 计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。 存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。 因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。 这样的方案可防止低优先级的设备变得“记忆不足”。 因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务 最迫切的要求。 此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

公开(公告)号：US06286083B1

公开(公告)日：2001-09-04

申请号：US09112000

申请日：1998-07-08

申请人： Kenneth T. Chin ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jeffrey C. Stevens ,  Michael J. Collins ,  C. Kevin Coffee

发明人： Kenneth T. Chin ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jeffrey C. Stevens ,  Michael J. Collins ,  C. Kevin Coffee

IPC分类号： G06F1318

CPC分类号： G06F13/1605

摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

摘要翻译： 计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。 存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。 因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。 这样的方案可防止低优先级的设备变得“记忆不足”。 因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务 最迫切的要求。 此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

公开(公告)号：US06279065B1

公开(公告)日：2001-08-21

申请号：US09090271

申请日：1998-06-03

申请人： Kenneth T. Chin ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  C. Kevin Coffee ,  Michael J. Collins

发明人： Kenneth T. Chin ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  C. Kevin Coffee ,  Michael J. Collins

IPC分类号： G06F1338

CPC分类号： G06F13/4239 ,  G06F13/4059

摘要： A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.

摘要翻译： 计算机系统包括CPU和由桥逻辑单元耦合的存储器件。 CPU到存储器写入请求（包括要写入的数据）暂时存储在桥逻辑单元的队列中。 在所有写入数据已经被存储在队列中并且可用于存储器装置之前，桥逻辑单元优选地开始到存储器装置的写周期。 通过尽早开始内存循环，减少了将所有写数据存储在队列中，然后从队列中取消队列数据所需的总时间。 因此，许多CPU到存储器写入事务被更有效地执行，并且通常以比先前可能的更少的延迟来执行。

公开(公告)号：US06247102B1

公开(公告)日：2001-06-12

申请号：US09047876

申请日：1998-03-25

申请人： Kenneth T. Chin ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jeffrey C. Stevens ,  C. Kevin Coffee ,  Michael J. Collins ,  John Larson

发明人： Kenneth T. Chin ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Jeffrey C. Stevens ,  C. Kevin Coffee ,  Michael J. Collins ,  John Larson

IPC分类号： G06F1314

CPC分类号： G06F13/1642 ,  G06F13/4036

摘要： A computer system includes a CPU, a memory device, two expansion buses, and a bridge logic unit coupling together the CPU, the memory device and the expansion buses. The CPU couples to the bridge logic unit via a CPU bus and the memory device couples to the bridge logic unit via a memory bus. The bridge logic unit generally routes bus cycle requests from one of the four buses to another of the buses while concurrently routing bus cycle requests to another pair of buses. The bridge logic unit preferably includes four interfaces, one each to the CPU, memory device and the two expansion buses. Each pair of interfaces are coupled by at least one queue; write requests are stored (or “posted”) in write queues and read data are stored in read queues. Because each interface can communicate concurrently with all other interfaces via the read and write queues, the possibility exists that a first interface cannot access a second interface because the second interface is busy processing read or write requests from a third interface, thus starving the first interface for access to the second interface. To remedy this starvation problem, the bridge logic unit prevents the third interface from posting additional write requests to its write queue, thereby permitting the first interface access to the second interface. Further, read cycles may be retried from one interface to allow another interface to complete its bus transactions.

摘要翻译： 计算机系统包括CPU，存储器件，两个扩展总线以及将CPU，存储器件和扩展总线耦合在一起的桥逻辑单元。 CPU通过CPU总线耦合到桥逻辑单元，存储器件通过存储器总线耦合到桥逻辑单元。 桥接逻辑单元通常将总线周期请求从四条总线之一路由到另一条总线，同时将总线周期请求转发到另一对总线。 桥逻辑单元优选地包括四个接口，每个接口连接到CPU，存储设备和两个扩展总线。 每对接口由至少一个队列耦合; 写入请求在写入队列中被存储（或“发布”），并且读取数据被存储在读取队列中。 因为每个接口可以通过读写队列与所有其他接口同时进行通信，所以存在第一接口无法访问第二接口的可能性，因为第二接口正忙于处理来自第三接口的读或写请求，从而使第一接口 用于访问第二个接口。 为了解决这个饥饿问题，桥接逻辑单元防止第三接口向其写入队列发布额外的写入请求，从而允许第一接口访问第二接口。 此外，可以从一个接口重试读周期，以允许另一接口完成其总线事务。