公开(公告)号：US20240387164A1

公开(公告)日：2024-11-21

申请号：US18691373

申请日：2022-01-28

Applicant: CANSEMI TECHNOLOGY INC.

Inventor： Ruijing HAN ,  Hui ZENG

IPC: H01L21/02

Abstract: The present invention provides a wafer cleaning method and a method for manufacturing semiconductor device. The wafer cleaning method includes: protonating a cleaning solution with a protonator; cleaning a wafer surface with the protonated cleaning solution so that the cleaned wafer surface carries an amount of negative charge smaller than an amount of negative charge present on a wafer surface that has been cleaned with a non-protonated cleaning solution and is covered with a liquid film of the cleaning solution; and purging the wafer surface with a drying gas to remove the liquid film from a center of the wafer surface towards its periphery. The technique proposed in the present invention is able to desirably suppress static electricity on a wafer surface and effectively reduce device failure that may be caused by static electricity, thereby increasing overall yield of integrated circuit manufacture.

公开(公告)号：US20240332395A1

公开(公告)日：2024-10-03

申请号：US18579269

申请日：2022-01-29

Applicant: GUANGZHOU CANSEMI TECHNOLOGY INC.

Inventor： Yohtz Julian CHANG ,  Yunbo CHEN ,  Canyang HUANG ,  Zeyong CHEN

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/94

CPC classification number: H01L29/66181 ,  H01L27/0207 ,  H01L29/94

Abstract: A semiconductor device structure and a method of forming the structure are disclosed. The semiconductor device structure includes a first capacitor and a second capacitor. The first capacitor is formed in a first redundant area, and the second capacitor is formed in a second redundant area. Since the first and second capacitors are formed in the respective redundant areas of the substrate, they will not unnecessarily occupy portions of a device area.

公开(公告)号：US20240319267A1

公开(公告)日：2024-09-26

申请号：US18575713

申请日：2022-01-29

Applicant: CANSEMI TECHNOLOGY INC.

Inventor： Zeyong CHEN ,  Zhengliang ZHOU

IPC: G01R31/30

CPC classification number: G01R31/3008

Abstract: An electrical leakage test structure and an electrical leakage testing method are disclosed. The electrical leakage test structure comprises: a substrate; a first well region and a second well region, which are both formed in the substrate; a first shallow trench isolation structure formed between the second and first well regions; a first source/drain region formed in the first well region; a plurality of second source/drain regions formed in the second well region; and a test gate formed on the substrate. In the electrical leakage testing method, a plurality of electrical leakage test structures with different designed dimensions are tested to perform leakage current evaluation on each electrical leakage test structure, and a designed dimension vs. leakage current relationship is developed based on the leakage current evaluation on each electrical leakage test structure, which reflects whether the internal design of a corresponding semiconductor device is associated with any problem such as parasitic leakage.

公开(公告)号：US20240379736A1

公开(公告)日：2024-11-14

申请号：US18691628

申请日：2022-01-28

Applicant: CANSEMI TECHNOLOGY INC.

Inventor： Xiang LIU ,  Jiaxi WANG

IPC: H01G4/30

Abstract: Disclosed are a metal-insulator-metal (MIM) capacitor structure and a method for fabricating the structure. The MIM capacitor structure includes: a substrate; a capacitor structure comprising a bottom metal layer, an interlayer dielectric layer and a top metal layer sequentially stacked over the substrate; an opening extending downward through the top metal layer into the interlayer dielectric layer; a recess located at a side wall of the opening, and extending from a bottom of the opening downward into the interlayer dielectric layer; and a sidewall spacer located in the opening, which extends over a side wall of the top metal layer and downward into the recess so as to fill it up, wherein the interlayer dielectric layer is made of the same material as the sidewall spacer. The MIM capacitor structure and a fabricating method therefor can improve the breakdown voltage of the MIM capacitor structure.

公开(公告)号：US20240202399A1

公开(公告)日：2024-06-20

申请号：US18555176

申请日：2021-12-28

Applicant: CANSEMI TECHNOLOGY INC.

Inventor： Ruijing HAN ,  Hui ZENG

IPC: G06F30/20 ,  G06F113/08 ,  G06F113/18 ,  H01L21/306

CPC classification number: G06F30/20 ,  H01L21/30604 ,  G06F2113/08 ,  G06F2113/18

Abstract: A method of modeling a wet etching process and a method of manufacturing a semiconductor device are disclosed. The modeling method includes: establishing partial differential equations of a reaction-diffusion system for chemical reactions involved in the wet etching process which is performed on a wafer surface using a mixed acid solution; obtaining formulas for the chemical reaction functions by applying the Brusselator model thereto; linearizing and expanding the formulas for the chemical reaction functions and thereby determining conditions for developing a chemical clock for the chemical reactions; calculating simulation parameters of the formulas for the chemical reaction functions; determining diffusion coefficients in the spatial diffusion terms, which allow formation of dome-shaped micro-cavities, thereby obtaining a mathematical model of the reaction-diffusion system for the chemical reactions involved in the wet etching process on the wafer surface. With the present invention, an optimal mixture ratio of the mixed acid solution can be rapidly and accurately determined, which enables formation of morphologically optimal dome-shaped micro-cavities on the wafer surface as a result of the etching process and hence improved performance of the semiconductor device being fabricated.