公开(公告)号：US20090244935A1

公开(公告)日：2009-10-01

申请号：US12054524

申请日：2008-03-25

Applicant: Ting-Chung HSIEH ,  Cheng-Yen Lin ,  Sheng-Chieh Chang ,  Min-Jon Lee

Inventor： Ting-Chung HSIEH ,  Cheng-Yen Lin ,  Sheng-Chieh Chang ,  Min-Jon Lee

IPC: H02M5/40

CPC classification number: H02M7/53873 ,  H03K7/06

Abstract: An inverter apparatus has an adaptable high-resolution voltage-to-frequency (V/f) control. The inverter apparatus receives an analog input signal and includes a first circuit, a second circuit, a third circuit, and a micro-controller unit. The first circuit processes a small-signal portion of the analog input signal with a larger voltage gain. The second and the third circuit both processes large-signal portions of the analog input signal with smaller voltage gains respectively. The three processed analog input signals of the first, the second, and the third circuits are converted into three digital output values respectively. The largest digital output value is selected by the micro-controller unit and supplied to a frequency operation unit for generating a corresponding output frequency.

Abstract translation: 逆变器装置具有适应性的高分辨率电压 - 频率（V / f）控制。 逆变器装置接收模拟输入信号，并且包括第一电路，第二电路，第三电路和微控制器单元。 第一电路以较大的电压增益处理模拟输入信号的小信号部分。 第二和第三电路分别以较小的电压增益处理模拟输入信号的大信号部分。 第一，第二和第三电路的三个处理的模拟输入信号分别转换成三个数字输出值。 最大的数字输出值由微控制器单元选择并提供给频率运算单元以产生相应的输出频率。

公开(公告)号：US20050233643A1

公开(公告)日：2005-10-20

申请号：US10825790

申请日：2004-04-16

Applicant: Wen-Jiunn Tsay ,  Cheng-Yu Wang ,  Cheng-Yen Lin

Inventor： Wen-Jiunn Tsay ,  Cheng-Yu Wang ,  Cheng-Yen Lin

IPC: H01R12/00 ,  H01R27/00 ,  H01R31/06

CPC classification number: H01R31/06 ,  H01R27/00

Abstract: Disclosed is a converter for interface card comprising a casing and a circuit board. The casing encapsulates the circuit board. The circuit board is provided with a connector at one end to be connected to a connector slot of a first interface protocol provided in a computer and a slot connector at the other end to be connected by a connector of a second interface protocol of an interface card. The circuit board is also provided with necessary wires and electronic components, to provide exchange of signals and electricity between a plurality of pins of said connector and a plurality of pins of said slot connector. The connector and the casing portion adjacent to said connector form a first size and the slot connector and the casing portion adjacent to said slot connector define a space of a second size. In one embodiment of this invention, the first size is smaller than the second size, while in another embodiment, the first size is greater than the second size.

Abstract translation: 公开了一种用于接口卡的转换器，包括壳体和电路板。 套管封装电路板。 电路板在一端设有连接器，以连接到设置在计算机中的第一接口协议的连接器插槽和另一端的插槽连接器，以由接口卡的第二接口协议的连接器连接 。 电路板还设置有必要的电线和电子部件，以在所述连接器的多个引脚和所述插槽连接器的多个引脚之间提供信号和电力的交换。 连接器和与所述连接件相邻的壳体部分形成第一尺寸，并且槽连接器和邻近所述槽连接器的壳体部分限定了第二尺寸的空间。 在本发明的一个实施例中，第一尺寸小于第二尺寸，而在另一实施例中，第一尺寸大于第二尺寸。

公开(公告)号：US20130080141A1

公开(公告)日：2013-03-28

申请号：US13614263

申请日：2012-09-13

Applicant: JENQ KUEN LEE ,  PO YU CHEN ,  CHENG YEN LIN

Inventor： JENQ KUEN LEE ,  PO YU CHEN ,  CHENG YEN LIN

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: The current disclosure discloses a power aware simulation system comprising an embedded multi-core simulation module, a power abstract interpretation module and a C power estimation (CPE) power profiling module. The embedded multi-core simulation module comprises a plurality of digital signal processors (DSP), an external memory and a direct memory access. Each of the plurality of DSPs comprises a DSP core, an instruction cache and a local memory. The power abstract interpretation module is coupled to the plurality of DSPs, the external memory, the DMA and the CPE profiling module, respectively.

Abstract translation: 本公开公开了一种功率感知模拟系统，其包括嵌入式多核仿真模块，功率抽象解释模块和C功率估计（CPE）功率分析模块。 嵌入式多核仿真模块包括多个数字信号处理器（DSP），外部存储器和直接存储器存取。 多个DSP中的每一个包括DSP内核，指令高速缓存和本地存储器。 功率抽象解释模块分别耦合到多个DSP，外部存储器，DMA和CPE分析模块。

公开(公告)号：US08137945B1

公开(公告)日：2012-03-20

申请号：US13150456

申请日：2011-06-01

Applicant: Rey-Ting Guo ,  Ya-Shan Cheng ,  Tzu-Hui Wu ,  Jian-Wen Huang ,  Hui-Lin Lai ,  Cheng-Yen Lin

Inventor： Rey-Ting Guo ,  Ya-Shan Cheng ,  Tzu-Hui Wu ,  Jian-Wen Huang ,  Hui-Lin Lai ,  Cheng-Yen Lin

IPC: C12N9/42 ,  C12N9/14

CPC classification number: C12N9/2437 ,  C12Y302/01004

Abstract: A thermostable cellulase having increased enzyme activity is disclosed. The cellulase comprises a modified amino acid sequence of SEQ ID NO: 2, wherein the tyrosine at position 61 is substituted with an amino acid selected from the group consisting of phenylalanine, alanine and glycine.

Abstract translation: 公开了具有增加的酶活性的热稳定纤维素酶。 纤维素酶包含SEQ ID NO：2的修饰的氨基酸序列，其中61位的酪氨酸被选自苯丙氨酸，丙氨酸和甘氨酸的氨基酸取代。

公开(公告)号：US07630222B2

公开(公告)日：2009-12-08

申请号：US12054524

申请日：2008-03-25

Applicant: Ting-Chung Hsieh ,  Cheng-Yen Lin ,  Sheng-Chieh Chang ,  Min-Jon Lee

Inventor： Ting-Chung Hsieh ,  Cheng-Yen Lin ,  Sheng-Chieh Chang ,  Min-Jon Lee

IPC: H02M7/539 ,  H02M7/5387

CPC classification number: H02M7/53873 ,  H03K7/06

Abstract: An inverter apparatus has an adaptable high-resolution voltage-to-frequency (V/f) control. The inverter apparatus receives an analog input signal and includes a first circuit, a second circuit, a third circuit, and a micro-controller unit. The first circuit processes a small-signal portion of the analog input signal with a larger voltage gain. The second and the third circuit both processes large-signal portions of the analog input signal with smaller voltage gains respectively. The three processed analog input signals of the first, the second, and the third circuits are converted into three digital output values respectively. The largest digital output value is selected by the micro-controller unit and supplied to a frequency operation unit for generating a corresponding output frequency.

Abstract translation: 逆变器装置具有适应性的高分辨率电压 - 频率（V / f）控制。 逆变器装置接收模拟输入信号，并且包括第一电路，第二电路，第三电路和微控制器单元。 第一电路以较大的电压增益处理模拟输入信号的小信号部分。 第二和第三电路分别以较小的电压增益处理模拟输入信号的大信号部分。 第一，第二和第三电路的三个处理的模拟输入信号分别转换成三个数字输出值。 最大的数字输出值由微控制器单元选择并提供给频率运算单元以产生相应的输出频率。

公开(公告)号：US08192974B1

公开(公告)日：2012-06-05

申请号：US13153618

申请日：2011-06-06

Applicant: Rey-Ting Guo ,  Jian-Wen Huang ,  Ya-Shan Cheng ,  Tzu-Hui Wu ,  Hui-Lin Lai ,  Cheng-Yen Lin

Inventor： Rey-Ting Guo ,  Jian-Wen Huang ,  Ya-Shan Cheng ,  Tzu-Hui Wu ,  Hui-Lin Lai ,  Cheng-Yen Lin

IPC: C12N9/42

CPC classification number: C12N9/2448

Abstract: A glucanase having increased enzyme activity and thermostability is disclosed. The glucanase comprises a modified amino acid sequence of SEQ ID NO: 2, wherein valine at position 18 is substituted with tyrosine and tryptophan at position 203 is substituted with tyrosine.

Abstract translation: 公开了具有增加的酶活性和热稳定性的葡聚糖酶。 葡聚糖酶包含SEQ ID NO：2的修饰的氨基酸序列，其中18位的缬氨酸被酪氨酸取代，203位的色氨酸被酪氨酸取代。