公开(公告)号：US5663921A

公开(公告)日：1997-09-02

申请号：US391159

申请日：1995-02-21

申请人： Luigi Pascucci ,  Marco Olivo ,  Carla Maris Golla

发明人： Luigi Pascucci ,  Marco Olivo ,  Carla Maris Golla

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32

CPC分类号： G11C7/22 ,  G11C16/32

摘要： A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.

摘要翻译： 电路产生灵活的时序，允许缓慢或快速的总体定时配置，以及通过提供两个（短或长）持续时间级别的预充电和检测间隔的两种配置。 为此，该电路包括一个可变的不对称传播线，该可变不对称传播线由基于存储的逻辑信号启用或禁用的一系列基本延迟元件组成，其状态在调试其中实施电路的存储器时被确定。