公开(公告)号：US07415033B2

公开(公告)日：2008-08-19

申请号：US10605049

申请日：2003-09-04

Applicant: Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

Inventor： Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

IPC: H04B7/212

CPC classification number: H04B7/2643

Abstract: In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n×p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract translation: 在适于根据用于最多N个可访问信道的动态时分多路复用接入方法交换n位帧的电信系统中，通过使用包括以下的电路来消除使用阴影时隙分配表：（a） nxp存储器块，用于存储通过指定n位帧的每个位位置属于哪个逻辑信道来描述不同时隙分配的时隙分配表，（b）具有一个位的粒度的N个字段的寄存器，每个 位指示与其相关联的相应逻辑信道的状态，以及（c）连接到存储器块和寄存器的逻辑电路，其根据状态位值使逻辑信道标识符发送到时隙分配器。

公开(公告)号：US5710869A

公开(公告)日：1998-01-20

申请号：US485337

申请日：1995-06-07

Applicant: Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

Inventor： Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063 ,  G06F15/00

CPC classification number: G06N3/063

Abstract: Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies the first free "or ready to learn" neuron circuit in the chain, based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network having daisy chain input and output signals complementary to each other. The daisy chain circuit includes a 1-bit register (601) controlled by a store enable signal (ST) which is active at initialization or, during the learning phase when a new neuron circuit is engaged. At initialization, all the Daisy registers of the chain are forced to a first logic value. The DCI input of the first daisy chain circuit in the chain is connected to a second logic value, such that after initialization, it is the ready to learn neuron circuit. In the learning phase, the ready to learn neuron's 1-bit daisy register contents are set to the second logic value by the store enable signal, it is said "engaged". As neurons are engaged, each subsequent neuron circuit in the chain then becomes the next ready to learn neuron circuit.

Abstract translation: 每个菊花链电路串联连接到两个相邻的神经元电路，使得所有的神经元电路形成链。 菊花链电路基于输入（DCI）和输出（DCI）的相应值来区分神经元电路的两种可能状态（被接合或自由）并且识别链中的第一个“准备学习”神经元电路 DCO）信号。 准备学习神经元电路是具有菊花链输入和输出信号彼此互补的神经网络的唯一神经元电路。 菊花链电路包括由初始化时有效的存储使能信号（ST）控制的1位寄存器（601），或者在新的神经元电路被接合时的学习阶段。 在初始化时，链的所有Daisy寄存器都被强制为第一个逻辑值。 链中第一个菊花链电路的DCI输入连接到第二个逻辑值，这样在初始化之后就可以学习神经元电路了。 在学习阶段，准备学习神经元的1位菊花寄存器内容通过存储使能信号设置为第二个逻辑值，它被称为“被接合”。 随着神经元的啮合，链中随后的每个神经元电路就成为下一个准备学习神经元电路的准备。

公开(公告)号：US07856030B2

公开(公告)日：2010-12-21

申请号：US12145719

申请日：2008-06-25

Applicant: Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

Inventor： Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

IPC: H04B7/212

CPC classification number: H04B7/2643

Abstract: In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n×p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract translation: 在适于根据用于最多N个可访问信道的动态时分多路复用接入方法交换n位帧的电信系统中，通过使用包括以下的电路来消除使用阴影时隙分配表：（a） n×p存储器块，用于存储通过指定n位帧的每个位位置属于哪个逻辑信道来描述不同时隙分配的时隙分配表，（b）具有一个位的粒度的N个字段的寄存器 每个位指示与其相关联的相应逻辑信道的状态，以及（c）连接到存储块和寄存器的逻辑电路，其根据状态位值使逻辑信道标识符发送到时隙分配器 。

公开(公告)号：US20080253404A1

公开(公告)日：2008-10-16

申请号：US12145719

申请日：2008-06-25

Applicant: Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

Inventor： Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

IPC: H04J3/00

CPC classification number: H04B7/2643

Abstract: In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n×p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract translation: 在适于根据用于最多N个可访问信道的动态时分多路复用接入方法交换n位帧的电信系统中，通过使用包括以下的电路来消除使用阴影时隙分配表：（a） nxp存储器块，用于存储通过指定n位帧的每个位位置属于哪个逻辑信道来描述不同时隙分配的时隙分配表，（b）具有一个位的粒度的N个字段的寄存器，每个 位指示与其相关联的相应逻辑信道的状态，以及（c）连接到存储器块和寄存器的逻辑电路，其根据状态位值使逻辑信道标识符发送到时隙分配器。

公开(公告)号：US5621863A

公开(公告)日：1997-04-15

申请号：US481591

申请日：1995-06-07

Applicant: Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

Inventor： Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06K9/66 ,  G06N3/00 ,  G06N3/06 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06K9/6272 ,  G06K9/00986 ,  G06N3/063

Abstract: In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.

Abstract translation: 在由多个神经元电路组成的神经网络中，生成本地结果信号的改进的神经元电路，例如， 的火灾类型，以及距离或类别类型的本地输出信号。 连接到传送输入数据（例如输入类别）和控制信号的总线的神经元电路。 多范围距离评估电路计算输入矢量和存储在R / W存储器电路中的原型矢量之间的距离D. 距离比较电路将该距离D与存储的原型矢量的实际影响场或其下限进行比较，以产生第一和第二比较信号。 识别电路处理比较信号，输入类别信号，局部类别信号和反馈信号，以产生表示神经元电路对输入矢量的响应的本地结果信号。 最小距离确定电路确定来自神经网络的所有神经元电路的所有计算距离中的最小距离Dmin，并产生距离类型的局部输出信号。 该电路可用于搜索和分类。 所有的神经元电路通过对所有的局部距离/类别进行OR运算来共同地产生反馈信号。 菊花链电路串联连接到两个相邻神经元电路的相应菊花链电路，以将神经元链接在一起。 菊花链电路还将神经元电路状态确定为自由或接合。 最后，上下文电路在反馈信号的产生中实现或抑制与其他神经元电路的神经元参与。

公开(公告)号：US20050053027A1

公开(公告)日：2005-03-10

申请号：US10605049

申请日：2003-09-04

Applicant: Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

Inventor： Patrick Lampin ,  Catherine Godefroy ,  Bernard Desrosiers ,  Yves Langlois

IPC: H04B7/212 ,  H04B7/26

CPC classification number: H04B7/2643

Abstract: The invention relates to a telecommunication system split in a plurality of subsystems that is adapted to exchange n-bit frames there between according to the dynamic time division multiplexing (TDM) access method. According to that method, the time is split in time slots, each one corresponding to one among N logical channels, wherein N is the maximum number of logical channels that can be simultaneously opened. To each logical channel (X, . . . ) is associated an identifier (LC X, . . . ) coded on p bits. In accordance with the present invention, the improved circuit (30) first comprises a n×p memory block (31) to store the time slot assignment (TSA) table which describes the different time slot assignments by specifying which logical channel each bit position of the n-bit TDM frame (Bit1 to Bitn) it belongs to. It further comprises a register (32) having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto: “assigned” when it has a first value or “unassigned” when it has another value. Finally, it comprises a logic circuit (33) connected to said memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract translation: 本发明涉及分离在多个子系统中的电信系统，其适于根据动态时分复用（TDM）接入方法在其间交换n位帧。 根据该方法，时间在时隙中分离，每个对应于N个逻辑信道中的一个，其中N是可以同时打开的逻辑信道的最大数量。 对每个逻辑信道（X，...）与在p位上编码的标识符（LC X，...）相关联。 根据本发明，改进的电路（30）首先包括一个nxp存储器块（31），用于存储描述不同时隙分配的时隙分配（TSA）表，其通过指定n的每个位的哪个逻辑信道 位数据帧（Bit1〜Bitn）。 它还包括具有1比特粒度的N个字段的寄存器（32），每个比特指示与之相关联的相应逻辑信道的状态：当它具有第一个值时被“分配”，或者当它具有另一个值时被“未分配”。 最后，它包括连接到所述存储器块和寄存器的逻辑电路（33），其根据状态位值启用或禁止逻辑信道标识符发送到时隙分配器。