公开(公告)号：US6156602A

公开(公告)日：2000-12-05

申请号：US368859

申请日：1999-08-06

申请人： Kai Shao ,  Shao-Fu Sanford Chu ,  Cerdin Lee

发明人： Kai Shao ,  Shao-Fu Sanford Chu ,  Cerdin Lee

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L28/56

摘要： A new method is provided for the creation of a resistive load in a semiconductor device whereby the semiconductor device further contains gate electrodes and a capacitor. Field isolation regions separate the active areas; a thin layer of gate oxide is created over these active regions. A first layer of poly is deposited, used for the gate electrode, for the bottom plate of the adjacent capacitor and for the resistor of high ohmic value. The gate poly is doped (in the first layer of poly); optionally the bottom plate of the capacitor can be doped. A dielectric layer is deposited for the dielectric of the capacitor; a second layer of poly is deposited, patterned and etched to form the capacitor top plate. The capacitor (dielectric and bottom plate), poly gates and the load resistor are patterned; the LDD regions for the transistors are created. The (gate, capacitor, resistor) spacers are formed, during and as part of the etch of the gate spacers a resistive spacer (called spacer since it serves to space or separate the two contact points of the resistor) is formed. The source/drain implants for the gate electrodes are performed thereby concurrently performing (self-aligned, due to the resistor spacer) implants for the contact regions of the resistor. All contacts (gate poly, source/drain and two contact points on the resistor) are salicided to achieve lower contact resistance.

摘要翻译： 提供了一种用于在半导体器件中产生电阻性负载的新方法，由此半导体器件还包含栅电极和电容器。 现场隔离区分开活动区域; 在这些活性区域上形成薄层的栅极氧化物。 沉积第一层poly，用于栅电极，用于相邻电容器的底板和高欧姆值的电阻。 掺杂多晶硅（在第一层聚合物中）; 可选地，可以掺杂电容器的底板。 为电容器的电介质沉积电介质层; 沉积第二层多晶硅，进行图案化和蚀刻以形成电容器顶板。 电容器（电介质和底板），多晶硅栅极和负载电阻器被图案化; 产生晶体管的LDD区域。 形成（栅极，电容器，电阻器）间隔物，在蚀刻栅极隔离物期间和作为蚀刻的一部分期间，形成电阻隔离物（称为间隔物，因为其用于空间或分离电阻器的两个接触点）。 执行栅电极的源极/漏极注入，由此同时对电阻器的接触区域进行（由于电阻器隔离物而自对准）植入物。 所有触点（栅极多晶硅，源极/漏极和电阻上的两个接触点）都被浸渍以实现较低的接触电阻。

公开(公告)号：US6159759A

公开(公告)日：2000-12-12

申请号：US443423

申请日：1999-11-19

申请人： Kai Shao ,  Cerdin Lee ,  Yi Xu ,  Shao-Fu Sanford Chu

发明人： Kai Shao ,  Cerdin Lee ,  Yi Xu ,  Shao-Fu Sanford Chu

IPC分类号： G02F1/1335 ,  G02F1/1362 ,  H01L21/00

CPC分类号： G02F1/133553 ,  G02F1/136277

摘要： A new method of forming liquid crystal displays has been achieved. Metal conductors are provided in an insulating layer overlying a semiconductor substrate. A first isolation layer is deposited. A first silicon nitride layer is deposited. The first silicon nitride layer is patterned to form openings for planned vias overlying the metal conductors. A second isolation layer is deposited. A second silicon nitride layer is deposited. The second silicon nitride layer is patterned to form masks overlying where dummy supports for the metal pixels are planned and to form openings to extend the planned vias. A third isolation layer is deposited. The third isolation layer is patterned to form openings for the planned metal pixels. The second isolation layer and the first isolation layer are etched through to complete the vias and the dummy supports. A metal layer is deposited filling the openings for the metal pixels, the dummy support, and the vias. The metal layer is polished down to the top surface of the third isolation layer to complete the metal pixels. A thin film passivation is deposited. A liquid crystal layer is deposited. A transparent image point electrode is formed to complete the liquid crystal display.

摘要翻译： 已经实现了一种形成液晶显示器的新方法。 金属导体设置在覆盖半​​导体衬底的绝缘层中。 沉积第一隔离层。 沉积第一氮化硅层。 图案化第一氮化硅层以形成覆盖金属导体的计划通孔的开口。 沉积第二隔离层。 沉积第二氮化硅层。 图案化第二氮化硅层以形成掩模，覆盖着金属像素的虚拟支撑被设计并形成扩展计划的通孔的开口。 沉积第三个隔离层。 图案化第三隔离层以形成用于计划的金属像素的开口。 蚀刻第二隔离层和第一隔离层以完成通孔和虚拟支撑。 沉积金属层，填充用于金属像素，虚拟支撑件和通孔的开口。 金属层被抛光到第三隔离层的顶表面以完成金属像素。 沉积薄膜钝化。 沉积液晶层。 形成透明图像点电极以完成液晶显示器。

公开(公告)号：US6117747A

公开(公告)日：2000-09-12

申请号：US435436

申请日：1999-11-22

申请人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

发明人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L28/60

摘要： A method for fabricating a metal-oxide-metal capacitor using a dual damascene process is described. A dielectric layer is provided overlying a semiconductor substrate. A dual damascene opening in the dielectric layer is filled with copper to form a copper via underlying a copper line. A first metal layer is deposited overlying the copper line and patterned to form a bottom capacitor plate contacting the copper line. A capacitor dielectric layer is deposited overlying the bottom capacitor plate. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top capacitor plate to complete fabrication of a metal-oxide-metal capacitor.

摘要翻译： 描述了使用双镶嵌工艺制造金属氧化物 - 金属电容器的方法。 提供覆盖在半导体衬底上的电介质层。 电介质层中的双镶嵌开口填充有铜，通过铜线下方形成铜。 沉积在铜线上的第一金属层被图案化以形成接触铜线的底部电容器板。 电容器电介质层沉积在底部电容器板上。 将第二金属层沉积在电容器介电层上并被图案化以形成顶部电容器板，以完成金属氧化物 - 金属电容器的制造。

公开(公告)号：US07714407B2

公开(公告)日：2010-05-11

申请号：US11847201

申请日：2007-08-29

申请人： Florin Udrea ,  Cerdin Lee

发明人： Florin Udrea ,  Cerdin Lee

IPC分类号： H01L29/00 ,  H01L21/8238

CPC分类号： H01L29/861 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

摘要： A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.

摘要翻译： 高电压/功率半导体器件具有具有高电压终端和低电压终端的半导体层。 漂移区域在高压端子和低压端子之间延伸。 在漂移区域的上方设置电介质层。 电导体延伸穿过漂移区域上方的电介质层的至少一部分，电导体连接或连接到高电压终端。 漂移区域具有位于电导体下方的多个沟槽。 沟槽横跨横穿半导体层的高压端子和低电压端子之间的方向横向延伸穿过漂移区域的至少一部分，每个沟槽包含电介质材料。 沟槽在电导体存在的情况下改善了器件中电场的分布。

公开(公告)号：US20090057831A1

公开(公告)日：2009-03-05

申请号：US11847201

申请日：2007-08-29

申请人： Florin Udrea ,  Cerdin Lee

发明人： Florin Udrea ,  Cerdin Lee

IPC分类号： H01L29/66 ,  H01L21/76

CPC分类号： H01L29/861 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

摘要： A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.

摘要翻译： 高电压/功率半导体器件具有具有高电压终端和低电压终端的半导体层。 漂移区域在高压端子和低压端子之间延伸。 在漂移区域的上方设置电介质层。 电导体延伸穿过漂移区域上方的电介质层的至少一部分，电导体连接或连接到高电压终端。 漂移区域具有位于电导体下方的多个沟槽。 沟槽横跨横穿半导体层的高压端子和低电压端子之间的方向横向延伸穿过漂移区域的至少一部分，每个沟槽包含电介质材料。 沟槽在电导体存在的情况下改善了器件中电场的分布。

公开(公告)号：US6124194A

公开(公告)日：2000-09-26

申请号：US439365

申请日：1999-11-15

申请人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

发明人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

IPC分类号： H01L21/768 ,  H01L23/525 ,  H07L29/00

CPC分类号： H01L21/7681 ,  H01L23/5252 ,  H01L2924/0002

摘要： A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via. Simultaneously, an anti-fuse metal line is formed over the fusing element to form an anti-fuse module within the anti-fuse area, and a dual damascene interconnect is formed over, and contacting with, the second metal line and within the interconnect area.

摘要翻译： 一种制造抗熔丝模块和双镶嵌互连结构的方法包括以下步骤。 提供具有被第一介电层覆盖的至少两个暴露的金属线的半导体结构。 第一金属线在反熔丝区内，第二金属线在互连区内。 第一金属通孔形成在反熔丝区域内的第一电介质层内，第一金属通孔接触第一金属线。 在第一介电层和第一金属通孔上沉积SiN层。 图案化SiN层以形成至少两个开口。 第一开口暴露第一金属通孔，第二开口暴露第二电介质层的第二金属线上方的一部分。 在图案化的SiN层状结构上沉积并图案化定影元件层，以在第一金属通孔之上形成定影元件。 同时，在熔断元件上方形成抗熔丝金属线，以在反熔丝区域内形成反熔丝模块，并且在第二金属线之间和互连区内形成双面镶嵌互连 。