Dynamic RFI mitigation
    2.
    发明申请
    Dynamic RFI mitigation 有权
    动态RFI缓解

    公开(公告)号:US20100158169A1

    公开(公告)日:2010-06-24

    申请号:US12317024

    申请日:2008-12-18

    IPC分类号: H03D1/04

    CPC分类号: H03D1/04

    摘要: Provided herein are different embodiments for performing radio frequency interference (RFI) mitigation in electronic devices such as mobile computing systems. In some embodiments, a dynamic RFI mitigation scheme allows for monitoring of wireless channels for RFI and to adaptively shift an identified RFI source (e.g., system clock) harmonics, e.g., either out of the on-channels or to a neutral position within the on-channels such as by using cost-function analysis.

    摘要翻译: 本文提供了用于在诸如移动计算系统的电子设备中执行射频干扰(RFI)缓解的不同实施例。 在一些实施例中,动态RFI缓解方案允许监视用于RFI的无线信道,并且自适应地将所识别的RFI源(例如,系统时钟)谐波(例如,在通道上或外部通道上的中性位置) 例如通过使用成本函数分析。

    Dynamic RFI detection
    3.
    发明授权
    Dynamic RFI detection 失效
    动态RFI检测

    公开(公告)号:US08280335B2

    公开(公告)日:2012-10-02

    申请号:US12217099

    申请日:2008-06-30

    IPC分类号: H04B1/10 H04B1/00

    CPC分类号: H04B1/1027

    摘要: Provided herein are different embodiments for performing radio frequency interference (RFI) detection in electronic devices such as mobile computing systems.

    摘要翻译: 本文提供了用于在诸如移动计算系统的电子设备中执行射频干扰(RFI)检测的不同实施例。

    Dynamic RFI detection
    4.
    发明申请
    Dynamic RFI detection 失效
    动态RFI检测

    公开(公告)号:US20090325530A1

    公开(公告)日:2009-12-31

    申请号:US12217099

    申请日:2008-06-30

    IPC分类号: H04B1/10

    CPC分类号: H04B1/1027

    摘要: Provided herein are different embodiments for performing radio frequency interference (RFI) detection in electronic devices such as mobile computing systems.

    摘要翻译: 本文提供了用于在诸如移动计算系统的电子设备中执行射频干扰(RFI)检测的不同实施例。

    ADAPTIVE CONTROL OF CLOCK SPREAD TO MITIGATE RADIO FREQUENCY INTERFERENCE
    5.
    发明申请
    ADAPTIVE CONTROL OF CLOCK SPREAD TO MITIGATE RADIO FREQUENCY INTERFERENCE 有权
    时钟传播的自适应控制以减轻无线电频率干扰

    公开(公告)号:US20090080583A1

    公开(公告)日:2009-03-26

    申请号:US11860374

    申请日:2007-09-24

    IPC分类号: H04L7/00

    CPC分类号: H04B15/02 H04B2215/067

    摘要: In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,自适应计时控制器确定系统时钟的时钟扩展,其将导致由无线电接收机接收的信道与系统时钟之间的最低总干扰。 时钟发生器响应于确定的时钟扩展来修改系统时钟的扩展。 描述和要求保护其他实施例。

    Closed Loop Adaptive Clock RFI Mitigation
    6.
    发明申请
    Closed Loop Adaptive Clock RFI Mitigation 有权
    闭环自适应时钟RFI缓解

    公开(公告)号:US20080240313A1

    公开(公告)日:2008-10-02

    申请号:US11694171

    申请日:2007-03-30

    IPC分类号: H03D1/04

    CPC分类号: H03D13/004 H04B15/04

    摘要: A method according to one embodiment for mitigating radio frequency interference by identifying system clocks, identifying active radio channels, measuring clock harmonics in or near the active radio channels, determining potential interference occurring if the clocks were moved to new fundamental frequencies, and shifting clock fundamental frequencies to reduce interference to the active radio channels based on existing interference and the potential interference of a plurality of new fundamental frequencies. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

    摘要翻译: 根据一个实施例的用于通过识别系统时钟,识别有源无线电信道,测量有源无线电信道中或附近的时钟谐波来减轻射频干扰的方法,确定如果时钟被移动到新的基本频率而发生的潜在干扰,并且移位时钟基准 基于现有干扰和多个新基频的潜在干扰来减少对有源无线电信道的干扰的频率。 当然,在不偏离本实施例的情况下,可以进行许多替代,变化和修改。

    Dynamic RFI detection
    7.
    发明授权

    公开(公告)号:US08965318B2

    公开(公告)日:2015-02-24

    申请号:US13602819

    申请日:2012-09-04

    IPC分类号: H04B1/10

    CPC分类号: H04B1/1027

    摘要: Provided herein are different embodiments for performing radio frequency interference (RFI) detection in electronic devices such as mobile computing systems.

    CROSSTALK AWARE DECODING FOR A DATA BUS
    8.
    发明申请
    CROSSTALK AWARE DECODING FOR A DATA BUS 审中-公开
    数据总线的CROSSTALK AWARE解码

    公开(公告)号:US20140181358A1

    公开(公告)日:2014-06-26

    申请号:US14142792

    申请日:2013-12-28

    IPC分类号: G06F13/40

    CPC分类号: G06F13/4072

    摘要: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a signaling module with a receiver, quantizer, and arithmetic circuit. The receiver receives a plurality of encoded line voltages or currents on a plurality of signal lines. The quantizer determines signal levels of each of the plurality of signal lines at a unit interval. The arithmetic circuit provides a plurality of digital output bits of the decoder based on the signal levels. Each one of the digital output bits is a mathematical combination of all of the signal levels.

    摘要翻译: 本文描述了用于解码编码数据的技术。 根据本技术的设备的示例包括具有接收器,量化器和运算电路的信令模块。 接收器在多个信号线上接收多个编码的线电压或电流。 量化器以单位间隔确定多条信号线中的每条信号线的信号电平。 算术电路基于信号电平提供解码器的多个数字输出位。 每个数字输出位都是所有信号电平的数学组合。

    CROSSTALK AWARE DECODING FOR A DATA BUS
    9.
    发明申请
    CROSSTALK AWARE DECODING FOR A DATA BUS 有权
    数据总线的CROSSTALK AWARE解码

    公开(公告)号:US20140181348A1

    公开(公告)日:2014-06-26

    申请号:US13844671

    申请日:2013-03-15

    IPC分类号: G06F13/40

    CPC分类号: G06F13/4004 G06F13/4022

    摘要: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.

    摘要翻译: 本文描述了用于解码编码数据的技术。 根据本技术的设备的示例包括耦合到多个信号线的接收信令模块。 信令模块包括接收器,用于在总线的多个信号线上接收多个编码线路电压或电流,其中多个编码线路电压中的每一个对应于数据的加权和。 信号模块包括一个比较器,用于以单位间隔确定每条线路的电压电平,并将电压电平转换成数字值。 信令模块包括将数字值与数字比特流相关联的查找表。

    Adaptive control of clock spread to mitigate radio frequency interference
    10.
    发明授权
    Adaptive control of clock spread to mitigate radio frequency interference 有权
    自适应控制时钟扩展以减轻射频干扰

    公开(公告)号:US08385485B2

    公开(公告)日:2013-02-26

    申请号:US13018725

    申请日:2011-02-01

    IPC分类号: H03D1/04

    CPC分类号: H04B15/02 H04B2215/067

    摘要: In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,自适应计时控制器确定系统时钟的时钟扩展,其将导致由无线电接收机接收的信道与系统时钟之间的最低总干扰。 时钟发生器响应于确定的时钟扩展来修改系统时钟的扩展。 描述和要求保护其他实施例。