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    Integrated circuit memory devices having dummy memory cells therein for inhibiting memory failures
    3.
    发明授权
    Integrated circuit memory devices having dummy memory cells therein for inhibiting memory failures 失效
    具有用于抑制存储器故障的虚拟存储器单元的集成电路存储器件

    公开(公告)号：US5867434A

    公开(公告)日：1999-02-02

    申请号：US912486

    申请日：1997-08-18

    Applicant: Chang-hag Oh ,  Sang-seok Kang ,  Jeon-hyung Lee ,  Jin-seok Lee

    Inventor： Chang-hag Oh ,  Sang-seok Kang ,  Jeon-hyung Lee ,  Jin-seok Lee

    IPC: H01L27/10 ,  H01L27/108 ,  G11C7/00

    CPC classification number: H01L27/10897

    Abstract: Integrated circuit memory devices contain an array of active memory cells and at least one column of dummy memory cells having missing electrical connections to either a dummy bit line and/or respective storage electrodes. The dummy memory cells are provided with missing electrical connections so that formation of stray electrical "shorts" between storage electrodes of dummy and active memory cells during fabrication do not cause memory failures when the memory devices are installed. In particular, integrated circuit memory devices are provided which comprise an array of active DRAM memory cells and a column of dummy DRAM memory cells. The active DRAM memory cells each contain electrical connections to a respective active bit line and a respective storage electrode, but the dummy DRAM memory cells are each devoid of an electrical connection to a dummy bit line and/or a respective storage electrode. Accordingly, the formation of a stringer (e.g., electrical short) between a storage capacitor of an active memory cell and a dummy memory cell does not result in a memory failure even if the word line coupled to the dummy memory cell is activated and the dummy bit line is biased at a potential which is different from the potential of the storage capacitor of the active memory cell.

    Abstract translation: 集成电路存储器件包含有效存储器单元的阵列和至少一列虚拟存储器单元，其具有与虚拟位线和/或相应存储电极的缺失的电连接。 虚拟存储器单元被提供有缺失的电连接，使得在制造期间在虚拟存储单元和有源存储单元的存储电极之间形成杂散电“短路”在安装存储器件时不会引起存储器故障。 特别地，提供了包括有源DRAM存储器单元阵列和虚拟DRAM存储器单元的列的集成电路存储器件。 有源DRAM存储单元各自包含与相应的有源位线和相应的存储电极的电连接，但虚拟DRAM存储单元各自没有与虚拟位线和/或相应存储电极的电连接。 因此，即使连接到虚拟存储器单元的字线被激活，在活动存储单元的存储电容器和虚拟存储单元之间形成纵梁（例如电短路）也不会导致存储器故障，并且虚拟 位线偏置于与有源存储单元的存储电容器的电位不同的电位。

    Semiconductor device
    4.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060132183A1

    公开(公告)日：2006-06-22

    申请号：US11312953

    申请日：2005-12-19

    Applicant: Dong-Jin Lim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Chang-Hag Oh

    Inventor： Dong-Jin Lim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Chang-Hag Oh

    IPC: H03K19/094

    CPC classification number: H03K19/00323

    Abstract: A semiconductor device that performs stable circuit operations is provided. The device includes: a pull-up driver for pulling up a first node in response to first states of input and control signals; a pull-down driver for pulling down a second node in response to a second state of the input signal; at least one fuse connected between the first node and the second node; a latch for generating an output signal to maintain the state of the second node; and a controller for generating the control signal that is maintained in a first state when the input signal is in the second state, and maintained in the first state and then transitioned to the second state after a predetermined delay time when the input signal is transitioned to the first state. In this construction, even if the fuse is incompletely cut during a process of cutting the fuse, the pull-up driver or the pull-down driver is turned off, thus preventing unnecessary current flow in advance.

    Abstract translation: 提供了执行稳定电路操作的半导体器件。 所述装置包括：用于响应于输入和控制信号的第一状态而拉起第一节点的上拉驱动器; 用于响应于所述输入信号的第二状态来拉下第二节点的下拉驱动器; 连接在第一节点和第二节点之间的至少一个熔丝; 用于产生输出信号以保持第二节点的状态的锁存器; 以及控制器，用于当输入信号处于第二状态时产生保持在第一状态的控制信号，并且当输入信号转换到预定的延迟时间后，保持在第一状态，然后转变到第二状态 第一个状态。 在这种结构中，即使在切断保险丝的过程中保险丝不完全切断，则上拉驱动器或下拉驱动器被关闭，从而防止事先不必要的电流流动。

    Integrated circuit memory devices having improved refresh mode addressing and methods of operating same
    5.
    发明授权
    Integrated circuit memory devices having improved refresh mode addressing and methods of operating same 有权
    具有改进的刷新模式寻址的集成电路存储器件及其操作方法

    公开(公告)号：US6002629A

    公开(公告)日：1999-12-14

    申请号：US206683

    申请日：1998-12-07

    Applicant: Jeon-Kyu Kim ,  Chang-Hag Oh ,  Choong-Sun Park ,  Jeon-Hyoung Lee

    Inventor： Jeon-Kyu Kim ,  Chang-Hag Oh ,  Choong-Sun Park ,  Jeon-Hyoung Lee

    IPC: G11C11/403 ,  G11C11/406 ,  G11C11/408 ,  G11C7/00

    CPC classification number: G11C11/4087 ,  G11C11/406

    Abstract: Integrated circuit memory devices include an array of memory cells and a row address generator circuit which generates first and second different sequences of addresses during first and second refresh modes, respectively, and also repeats at least one of the addresses in the first sequence as an address in the second sequence when transitioning from the first refresh mode to the second refresh mode. The generator circuit may also perform the function of generating row addresses during the first and second refresh modes with the most significant bit of a row address being toggled with each consecutive row address during the first refresh mode. The first refresh mode may be a CAS-before-RAS refresh mode, the second refresh mode may be a self-refresh mode and the address in at least one of the first and second periods of the self-refresh mode may be equivalent to an address in the last period of a preceding CAS-before-RAS refresh mode when transitioning from the first refresh mode to the second refresh mode. This repetition in addressing prevents one or more row of memory cells from being skipped when transitioning from one refresh mode to another refresh mode.

    Abstract translation: 集成电路存储器件包括存储器单元阵列和行地址发生器电路，其分别在第一和第二刷新模式期间产生第一和第二不同的地址序列，并且还将第一序列中的至少一个地址重复为地址 在从第一刷新模式转换到第二刷新模式的第二序列中。 发生器电路还可以执行在第一和第二刷新模式期间产生行地址的功能，其中在第一刷新模式期间行地址的最高有效位与每个连续行地址切换。 第一刷新模式可以是CAS-before-RAS刷新模式，第二刷新模式可以是自刷新模式，并且自刷新模式的第一和第二周期中的至少一个中的地址可以等效于 在从第一刷新模式转换到第二刷新模式时，在先前的CAS-before-RAS刷新模式的最后期间中的地址。 这种在寻址中的重复防止当从一个刷新模式转换到另一刷新模式时跳过一行或多行存储器单元。

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