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1.发明授权Tri-state bus contention circuit preventing false switching caused by poor synchronization 失效三态总线竞争电路防止由于同步不良引起的错误切换
公开(公告)号：US6134620A
公开(公告)日：2000-10-17
申请号：US52246
申请日：1998-03-31
IPC分类号： G06F13/40
CPC分类号： G06F13/4072
摘要： A method of avoiding contention on a communications bus using an improved tri-state driver, which negates one of the internal driver signals during a restore region of the driver cycle, such that the driver cannot switch to the high state when there is poor synchronization that delays one of the internal driver signals. Restoring logic provides a first logic signal and a second logic signal. An input gate is asserted to an active level in response to the first logic signal, and gating logic conditionally enables the input gate in response to the second signal.
摘要翻译： 一种使用改进的三态驱动器避免在通信总线上的争用的方法，其在驱动器周期的恢复区域期间否定内部驱动器信号之一，使得当差的同步时，驱动器不能切换到高状态 延迟内部驱动器信号之一。 恢复逻辑提供第一逻辑信号和第二逻辑信号。 响应于第一逻辑信号将输入门断言为有效电平，并且门控逻辑有条件地使得输入门响应于第二信号。
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公开(公告)号：US6140854A
公开(公告)日：2000-10-31
申请号：US236775
申请日：1999-01-25
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07 , H03L7/089
摘要： A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).
摘要翻译： 系统（50）具有移位延迟电路（60），其提供用于延迟源时钟的可变延迟和延迟锁定环（DLL）（70），延迟锁定环（DLL）（70）包括延迟线（72），延迟线（72）提供可变延迟以延迟 源时钟。 延迟线（18）具有由计数器（74）变化的延迟。 计数器（74）增加以改变延迟。 移位延迟电路（60）基于与源时钟具有已知关系的参考时钟（GCLK）的半周期。 源时钟的总延迟是通过移位延迟电路（60）和延迟线（72）提供的总延迟的组合。 由于使用了移位延迟电路（60），因此在集成电路中需要较大量的管芯面积的延迟线（72）的尺寸可以更小。
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公开(公告)号：US06294938B1
公开(公告)日：2001-09-25
申请号：US09552824
申请日：2000-04-20
IPC分类号： H03L706
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07 , H03L7/089
摘要： A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).
摘要翻译： 系统（50）具有移位延迟电路（60），其提供用于延迟源时钟的可变延迟和延迟锁定环（DLL）（70），延迟锁定环（DLL）（70）包括延迟线（72），延迟线（72）提供可变延迟以延迟 源时钟。 延迟线（18）具有由计数器（74）变化的延迟。 计数器（74）增加以改变延迟。 移位延迟电路（60）基于与源时钟具有已知关系的参考时钟（GCLK）的半周期。 源时钟的总延迟是通过移位延迟电路（60）和延迟线（72）提供的总延迟的组合。 由于使用了移位延迟电路（60），因此在集成电路中需要较大量的管芯面积的延迟线（72）的尺寸可以更小。
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4.发明授权Method and apparatus to reduce system bus latency on a cache miss with address acknowledgments 失效通过地址确认减少高速缓存未命中的系统总线延迟的方法和装置公开(公告)号：US06266741B1
公开(公告)日：2001-07-24
申请号：US09094905
申请日：1998-06-15
IPC分类号： G06F1200
CPC分类号： G06F12/0897
摘要： A method of providing a value to a cache used in a computer system, by transmitting the value from a system memory device to a lower level (e.g., L2) of the cache using a system bus, acknowledging the forwarding of the address from the lower level of the cache after said transmitting of the value, and acknowledging the forwarding of the address from a higher level (e.g., on-board) of the cache, in response to said transmitting step. The acknowledging of the forwarding of the address from the higher level of the cache, can occur prior to the acknowledgment of the forwarding of the address from the lower level of the cache. The value is transmitted from the lower level of the cache to the higher level of the cache using the higher level bus, in response to said acknowledgement of the forwarding of the address from the higher level of the cache, and this latter transmission can also occur prior to said acknowledgment of the forwarding of the address from the lower level of the cache. This approach results in reduced memory access latency with L2 cache misses, and improves address bus utilization on the higher level bus.
摘要翻译： 通过使用系统总线将值从系统存储器件发送到高速缓存的较低级（例如L2），向计算机系统中使用的高速缓存器提供值的方法，确认地址从较低级 在发送所述值之后的所述高速缓存的级别，以及响应于所述发送步骤，确认所述地址从所述高速缓存的较高级别（例如，板上）转发。 从高速缓存的较高级别转发地址的确认可以在从缓存的较低级别转发地址之前发生。 响应于来自高速缓存的较高级别的地址转发的所述确认，该值从高速缓存的较低级别发送到高级总线的较高级别，并且后一种传输也可以发生 在所述确认从高速缓存的较低级别转发地址之前。 这种方法导致具有L2高速缓存未命中的存储器访问延迟减少，并且提高了较高级总线上的地址总线利用率。
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