Reducing the format time for bit alterable memories
    1.
    发明授权
    Reducing the format time for bit alterable memories 有权
    减少位可变存储器的格式时间

    公开(公告)号:US07831762B2

    公开(公告)日:2010-11-09

    申请号:US11605572

    申请日:2006-11-29

    Applicant: Cheng Zheng

    Inventor: Cheng Zheng

    CPC classification number: G11C13/0004 G06F12/0246

    Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.

    Abstract translation: 在可位可变存储器中,特定块的特定头可以被编程到特定代码以指示该块被认为是空的。 这节省了在块的头部和数据部分中重置所有位的时间。

    Method and apparatus for locking a plurality of display synchronization signals
    2.
    发明授权
    Method and apparatus for locking a plurality of display synchronization signals 有权
    用于锁定多个显示同步信号的方法和装置

    公开(公告)号:US06535208B1

    公开(公告)日:2003-03-18

    申请号:US09654671

    申请日:2000-09-05

    CPC classification number: H04N5/073 G09G5/12 H04N9/641

    Abstract: A method and apparatus locks a plurality of display synchronization signals, such as horizontal synchronization signals and a vertical synchronization signals, from a plurality of display output devices, such as a plurality of graphics processors. The method and apparatus digitally adjusts a vertical synchronization signal associated with a first display output device, with respect to a vertical synchronization signal associated with a second graphic output device until a crossover is detected between the first and second vertical synchronization signals. This provides a type of coarse synchronization. In response to detection of the first crossover, the method and apparatus digitally adjusts a horizontal synchronization signal associated with the first display output device with respect to a horizontal synchronization signal associated with the second display device to align the synchronization signals. The adjustment of the horizontal synchronization signals provides a fine synchronization adjustment.

    Abstract translation: 方法和装置从诸如多个图形处理器的多个显示输出装置中锁定多个显示同步信号,诸如水平同步信号和垂直同步信号。 所述方法和装置相对于与第二图形输出装置相关联的垂直同步信号,数字地调节与第一显示输出装置相关联的垂直同步信号,直到在第一和第二垂直同步信号之间检测到交叉。 这提供了一种粗略的同步。 响应于第一交叉点的检测,该方法和装置相对于与第二显示装置相关联的水平同步信号数字地调整与第一显示输出装置相关联的水平同步信号,以对齐同步信号。 水平同步信号的调整提供了精细的同步调整。

    AUTHENTICATION METHODS
    3.
    发明申请
    AUTHENTICATION METHODS 审中-公开
    认证方法

    公开(公告)号:US20110162051A1

    公开(公告)日:2011-06-30

    申请号:US12690652

    申请日:2010-01-20

    Abstract: A computer readable storage medium has computer-executable instructions for causing a computer system to perform a method. The method includes receiving authentication information from an electronic device; identifying the electronic device based on device information for the electronic device; locating an entry associated with a combination of the authentication information and the electronic device, the entry including a count of the number of times the authentication information failed authentication during a specified time interval; and locking out the combination if the count reaches a threshold value, thus blocking the authentication information from accessing a target.

    Abstract translation: 计算机可读存储介质具有用于使计算机系统执行方法的计算机可执行指令。 该方法包括从电子设备接收认证信息; 基于所述电子设备的设备信息识别所述电子设备; 定位与所述认证信息和所述电子设备的组合相关联的条目,所述条目包括在指定时间间隔期间认证信息失败认证的次数的计数; 如果计数达到阈值,则锁定组合,从而阻止认证信息访问目标。

    Trapping Filter for Blood Vessel
    4.
    发明申请
    Trapping Filter for Blood Vessel 审中-公开
    血管捕获过滤器

    公开(公告)号:US20070233174A1

    公开(公告)日:2007-10-04

    申请号:US11554055

    申请日:2006-10-30

    Abstract: The present invention provides the filter from the wire elements only, which certainly traps the thrombus and others, and easily visualizes from extra-corporeal and trapping system. The solution set forth in the present invention involves an expandable trapping filter, which is consist of plural knitted metallic wires with elastic or shape memory nature. The filter has two bundled parts in the distal and proximal ends of plural wires. When this filter expands at the intended tubular cavity of body part, each wire flips over to form parasol shape moving proximal bundled to distal bundled to catch a thrombus and others. Trapping system is deliverable from the distal edge of sheath which is interiorly loaded and is able to move in and out by the shaft movement along the penetrating shaft with the of proximal bundle immobilization.

    Abstract translation: 本发明仅提供来自线元件的过滤器,其可以捕获血栓和其它物质,并且容易从外部物质和捕获系统可视化。 本发明提出的解决方案涉及一种可膨胀捕获过滤器,其由具有弹性或形状记忆性质的多根针织金属线组成。 过滤器在多根线的远端和近端具有两个捆扎部分。 当该过滤器在身体部分的预期管状空腔处膨胀时,每根丝线翻转以形成移动的近侧捆绑形式的近侧捆绑到远端捆绑以捕获血栓等。 捕集系统可以从内部装载的护套的远端边缘输送,并且能够通过近端束固定的沿着穿透轴的轴运动进出。

    Bit-Alterable, Non-Volatile Memory Management
    5.
    发明申请
    Bit-Alterable, Non-Volatile Memory Management 审中-公开
    位可变,非易失性内存管理

    公开(公告)号:US20080285332A1

    公开(公告)日:2008-11-20

    申请号:US10581754

    申请日:2005-12-30

    CPC classification number: G06F12/023 G11C13/0004

    Abstract: Methods and apparatuses for storage of data in bit-alterable, non-volatile memories. In some embodiments, an array of memory locations implemented as bit-alterable, non-volatile memory configured as a plurality of blocks of memory locations; and control circuitry coupled with the array of memory locations to cause a block of data to be stored in the array of memory spanning a boundary between a first block of memory locations and a second block of memory locations. One or more processors access system data during initialization of an electronic system by retrieving data from a pre-selected location in a bit-alterable, non-volatile memory without scanning multiple memory locations to locate the system data.

    Abstract translation: 用于将数据存储在位可变的非易失性存储器中的方法和装置。 在一些实施例中,存储器位置的阵列被实现为被配置为存储器位置的多个块的可变位的非易失性存储器; 以及与存储器位置阵列耦合的控制电路,以使数据块存储在跨越存储器位置的第一块和第二存储单元块之间的边界的存储器阵列中。 一个或多个处理器在电子系统的初始化期间通过从位可改变的非易失性存储器中的预选位置检索数据而不扫描多个存储器位置来定位系统数据来访问系统数据。

    Reducing the format time for bit alterable memories
    6.
    发明申请
    Reducing the format time for bit alterable memories 有权
    减少位可变存储器的格式时间

    公开(公告)号:US20080123441A1

    公开(公告)日:2008-05-29

    申请号:US11605572

    申请日:2006-11-29

    Applicant: Cheng Zheng

    Inventor: Cheng Zheng

    CPC classification number: G11C13/0004 G06F12/0246

    Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.

    Abstract translation: 在可位可变存储器中,特定块的特定头可以被编程到特定代码以指示该块被认为是空的。 这节省了在块的头部和数据部分中重置所有位的时间。

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