公开(公告)号：US20070035505A1

公开(公告)日：2007-02-15

申请号：US11362213

申请日：2006-02-24

申请人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

发明人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3648 ,  G09G2310/0286 ,  G09G2320/0219

摘要： A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

摘要翻译： 具有一系列级联移位寄存器的移位寄存器电路包括耦合到前级移位寄存器的输出信号的第一晶体管，耦合到第一晶体管的第二晶体管，输出和第一时钟信号以及下拉 模块耦合到输出，前级和后级移位寄存器的输出信号，第二和第三电压电平。 当第二晶体管导通并且第一时钟信号处于高电压电平时，输出处于第一电压电平。 当后级移位寄存器的信号处于第一电压电平时，输出处于第三电压电平。

公开(公告)号：US20090009462A1

公开(公告)日：2009-01-08

申请号：US11853026

申请日：2007-09-11

申请人： Chao-Ching Hsu ,  Cheng-Liang Ma ,  Wei-cheng Lin

发明人： Chao-Ching Hsu ,  Cheng-Liang Ma ,  Wei-cheng Lin

IPC分类号： G09G3/36

CPC分类号： G02F1/133305 ,  G02F1/1345 ,  G09G3/3611 ,  G09G3/3666 ,  G09G2300/0426 ,  G09G2310/0281 ,  G09G2330/021

摘要： An LCD panel including a liquid crystal cell array, gate driving integrated circuits (ICs), first source driving ICs, second source driving ICs and a timing control circuit is provided. The liquid crystal cell array has a first display area and a second display area. The first and the second source driving ICs are electrically connected with the first and the second display areas, respectively, while the timing control circuit is electrically connected with the source and the gate driving ICs. The LCD panel is driven by writing data into the first display area through the first source driving ICs via a first receiving/transmitting mode and writing data into the second display area through the second source driving ICs via a second receiving/transmitting mode. The first data receiving/transmitting mode is different from the second receiving/transmitting mode.

摘要翻译： 提供了包括液晶单元阵列的LCD面板，栅极驱动集成电路（IC），第一源极驱动IC，第二源极驱动IC和定时控制电路。 液晶单元阵列具有第一显示区域和第二显示区域。 第一和第二源极驱动IC分别与第一和第二显示区域电连接，同时定时控制电路与源极和栅极驱动IC电连接。 通过第一接收/发送模式通过第一源极驱动IC将数据写入第一显示区域并通过第二接收/发送模式通过第二源极驱动IC将数据写入第二显示区域来驱动LCD面板。 第一数据接收/发送模式与第二接收/发送模式不同。

公开(公告)号：US07317780B2

公开(公告)日：2008-01-08

申请号：US11362213

申请日：2006-02-24

申请人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

发明人： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

IPC分类号： G11K19/00 ,  H03K19/00

CPC分类号： G11C19/28 ,  G09G3/3648 ,  G09G2310/0286 ,  G09G2320/0219

摘要： A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

摘要翻译： 具有一系列级联移位寄存器的移位寄存器电路包括耦合到前级移位寄存器的输出信号的第一晶体管，耦合到第一晶体管的第二晶体管，输出和第一时钟信号以及下拉 模块耦合到输出，前级和后级移位寄存器的输出信号，第二和第三电压电平。 当第二晶体管导通并且第一时钟信号处于高电压电平时，输出处于第一电压电平。 当后级移位寄存器的信号处于第一电压电平时，输出处于第三电压电平。