公开(公告)号：US20110260754A1

公开(公告)日：2011-10-27

申请号：US13178694

申请日：2011-07-08

申请人： Chenkong Teh ,  Hiroyuki Hara

发明人： Chenkong Teh ,  Hiroyuki Hara

IPC分类号： H03K19/096

CPC分类号： H03K3/356191

摘要： A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.

摘要翻译： 一种半导体集成电路器件，包括：由基于输入信号对充电点充电的第一晶体管构成的第一反相器和基于输入信号对放电点进行放电的第二晶体管; P型第三晶体管和N型第四晶体管，其漏极源路径并联设置在充电点和放电点之间; 以及第二反相器，被配置为反转充电点或放电点的电位，并将反相电势提供给第三和第四晶体管的栅极，并从充电点或放电点获得输入信号的延迟信号。 半导体集成电路器件以小的面积确保足够的延迟时间。

公开(公告)号：US20100315127A1

公开(公告)日：2010-12-16

申请号：US12701730

申请日：2010-02-08

申请人： Chenkong Teh ,  Hiroyuki Hara

发明人： Chenkong Teh ,  Hiroyuki Hara

IPC分类号： H03K19/094 ,  H03K19/20

CPC分类号： H03K3/356191

摘要： A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.

摘要翻译： 一种半导体集成电路器件，包括：由基于输入信号对充电点充电的第一晶体管构成的第一反相器和基于输入信号对放电点进行放电的第二晶体管; P型第三晶体管和N型第四晶体管，其漏极源路径并联设置在充电点和放电点之间; 以及第二反相器，被配置为反转充电点或放电点的电位，并将反相电势提供给第三和第四晶体管的栅极，并从充电点或放电点获得输入信号的延迟信号。 半导体集成电路器件以小的面积确保足够的延迟时间。

公开(公告)号：US08415982B2

公开(公告)日：2013-04-09

申请号：US13178694

申请日：2011-07-08

申请人： Chenkong Teh ,  Hiroyuki Hara

发明人： Chenkong Teh ,  Hiroyuki Hara

IPC分类号： H03K19/096 ,  H03K19/094 ,  H03K19/20 ,  H03K3/00 ,  H03K5/12 ,  H03B1/00

CPC分类号： H03K3/356191

摘要： A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.

摘要翻译： 一种半导体集成电路器件，包括：由基于输入信号对充电点充电的第一晶体管构成的第一反相器和基于输入信号对放电点进行放电的第二晶体管; P型第三晶体管和N型第四晶体管，其漏极源路径并联设置在充电点和放电点之间; 以及第二反相器，被配置为反转充电点或放电点的电位，并将反相电势提供给第三和第四晶体管的栅极，并从充电点或放电点获得输入信号的延迟信号。 半导体集成电路器件以小的面积确保足够的延迟时间。

公开(公告)号：US07999575B2

公开(公告)日：2011-08-16

申请号：US12701730

申请日：2010-02-08

申请人： Chenkong Teh ,  Hiroyuki Hara

发明人： Chenkong Teh ,  Hiroyuki Hara

IPC分类号： H03K19/20 ,  H03K19/096 ,  H03K3/356

CPC分类号： H03K3/356191

摘要： A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.

摘要翻译： 一种半导体集成电路器件，包括：由基于输入信号对充电点充电的第一晶体管构成的第一反相器和基于输入信号对放电点进行放电的第二晶体管; P型第三晶体管和N型第四晶体管，其漏极源路径并联设置在充电点和放电点之间; 以及第二反相器，被配置为反转充电点或放电点的电位，并将反相电势提供给第三和第四晶体管的栅极，并从充电点或放电点获得输入信号的延迟信号。 半导体集成电路装置以小的面积确保足够的延迟时间。