公开(公告)号：US5299309A

公开(公告)日：1994-03-29

申请号：US816702

申请日：1992-01-02

Applicant: Bor-Chuan Kuo ,  Cheun-Song Lin ,  Lie-Der Lin ,  Shu-Wei Wang

Inventor： Bor-Chuan Kuo ,  Cheun-Song Lin ,  Lie-Der Lin ,  Shu-Wei Wang

IPC: G06F3/14 ,  G06T17/00 ,  G09G5/14 ,  G06F15/20

CPC classification number: G06F3/14 ,  G06T17/00 ,  G09G5/14

Abstract: A host computer, a graphics processor which receives and executes commands generated by the host computer, a display memory for storing display data, and a display device for displaying the display data are provided. A graphics context is also provided in which the parameters of a current image are stored. A processing unit for receiving and executing the graphics commands issued by the host computer and for converting the parameters stored in the graphics context into the display data, and a drawing unit for storing the display data in the display memory are also provided. Furthermore, a shared memory is provided which is directly accessible to the host computer so that it can write the parameters of a next graphics command into the shared memory while the graphics processor is executing a current command. The shared memory is also directly accessible to the graphics processor so that it can receive the parameters of the next graphics command to be executed directly from the shared memory. In a preferred embodiment, transfers of the graphics parameters between the graphics context and the shared memory are accomplished by employing a bit-block transfer method and a mask register stored in the graphics context.

Abstract translation: 主计算机，接收和执行由主计算机产生的命令的图形处理器，用于存储显示数据的显示存储器和用于显示显示数据的显示装置。 还提供了存储当前图像的参数的图形上下文。 一种处理单元，用于接收和执行由主计算机发出的图形命令，并将存储在图形上下文中的参数转换成显示数据，还提供了一种用于将显示数据存储在显示存储器中的绘图单元。 此外，提供了一种共享存储器，其可以直接访问主计算机，使得它可以在图形处理器执行当前命令时将下一个图形命令的参数写入共享存储器。 共享存储器也可以直接访问图形处理器，使得它可以接收要从共享存储器直接执行的下一个图形命令的参数。 在优选实施例中，图形上下文和共享存储器之间的图形参数的传送通过采用存储在图形上下文中的位块传送方法和掩码寄存器来实现。

公开(公告)号：US5268681A

公开(公告)日：1993-12-07

申请号：US772499

申请日：1991-10-07

Applicant: Cheun-Song Lin ,  Bor-Chuan Kuo ,  Rong-Chung Chen

Inventor： Cheun-Song Lin ,  Bor-Chuan Kuo ,  Rong-Chung Chen

IPC: G09G5/39 ,  G09G5/395 ,  G09G1/02

CPC classification number: G09G5/395

Abstract: A video display system includes a frame buffer comprising five sets of one or more VRAMs. An address generator for generating address locations in the frame buffer generates chip select, row select and column select address signals. Because the frame buffer comprises five sets of VRAMs, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memory capacity in the frame buffer.

Abstract translation: 视频显示系统包括帧缓冲器，该帧缓冲器包括五组一个或多个VRAM。 用于在帧缓冲器中产生地址位置的地址发生器产生片选，行选择和列选地址信号。 由于帧缓冲器包括五组VRAM，所以产生地址信号需要执行五分之一的操作。 因此，地址发生器包括唯一的除以5的电路，其中除法由一系列的加法和乘法执行。 与常规系统相比，本发明的视频系统更有效地利用帧缓冲器中的存储器容量。

公开(公告)号：US06792602B2

公开(公告)日：2004-09-14

申请号：US09739756

申请日：2000-12-20

Applicant: Cheun-Song Lin ,  Cheng-Yu Chen ,  Ching-Lung Tsai ,  Cheu-Wei Hsu

Inventor： Cheun-Song Lin ,  Cheng-Yu Chen ,  Ching-Lung Tsai ,  Cheu-Wei Hsu

IPC: G06F300

CPC classification number: G06F13/385

Abstract: The invention provides a solution/device for controlling external parameters by use of the same data cable and specific software to transfer/receive messages and monitor/control external parameters in a system. Additionally, the invention is compatible with ATA/ATAPI by using the ATA protocol or side-band protocol to make a main system communicate with other device(s) through an ATA/ATAPI device's data cable. Also, the invention uses the system's data cables and a non-standard controlling sequence to transfer and receive messages by the same cable to connect with the external devices for monitoring/controlling external parameters. Hence, the number of data wires needed is reduced. Also, the invention can decrease the manufacture costs and get a better heating dissipation.

Abstract translation: 本发明提供了一种用于通过使用相同数据电缆和特定软件来控制外部参数以在系统中传送/接收消息和监视/控制外部参数的解决方案/设备。 此外，本发明通过使用ATA协议或边带协议使ATA / ATAPI与ATA / ATAPI设备的数据电缆与其他设备通信，与ATA / ATAPI兼容。 此外，本发明使用系统的数据电缆和非标准控制顺序，通过相同的电缆传送和接收消息，以与外部设备连接，以监控/控制外部参数。 因此，所需的数据线的数量减少。 此外，本发明可以降低制造成本并获得更好的散热。

公开(公告)号：US5638467A

公开(公告)日：1997-06-10

申请号：US62410

申请日：1993-05-14

Applicant: Well-Chen Chua ,  Lie-Der Lin ,  Shih-Pao Sun ,  Cheun-Song Lin

Inventor： Well-Chen Chua ,  Lie-Der Lin ,  Shih-Pao Sun ,  Cheun-Song Lin

IPC: G06T3/40 ,  G06K9/32

CPC classification number: G06T3/4023

Abstract: A bit-reversing method and system are disclosed for linearly scaling an image frame horizontally, vertically or both. The system includes a counter circuit for outputting the current frame-column number of the currently scanned pixel and the current frame-row number of the currently scanned frame-row. The numbers are bit reversed in a converter circuit. The bit-reversed current frame-column number is compared in a comparator circuit to a horizontal scaling constant which equals the number of pixels to be discarded in each frame-row of the image frame. The bit-reversed current frame-row number is compared in the comparator circuit to a vertical scaling constant which equals the number of frame-rows of the image frame to be discarded. If the bit-reversed current frame-row number is greater than the vertical scaling constant then the comparator circuit outputs appropriate signals to a scaling controller and an address generator for storing the currently scanned frame-row in a frame buffer. Otherwise, the comparator circuit outputs appropriate signals for discarding the currently scanned frame-row. Likewise, if the bit-reversed current column number is greater than the horizontal scaling constant, the comparator circuit outputs appropriate signals to the scaling controller and address generator for storing the currently scanned pixel in the frame buffer. Otherwise, the comparator circuit outputs appropriate signals for discarding the currently scanned pixel.

Abstract translation: 公开了一种位反转方法和系统，用于水平，垂直或两者直线地缩放图像帧。 该系统包括用于输出当前扫描像素的当前帧列号和当前扫描帧行当前帧行号的计数器电路。 这些数字在转换器电路中是相反的。 在比较器电路中将比特反转的当前帧列号比较为等于在帧帧的每个帧行中要丢弃的像素数量的水平缩放常数。 在比较器电路中将比特反转的当前帧行号比较为等于要丢弃的图像帧的帧行数的垂直缩放常数。 如果位反转的当前帧行数大于垂直缩放常数，则比较器电路将适当的信号输出到缩放控制器和用于将当前扫描的帧行存储在帧缓冲器中的地址发生器。 否则，比较器电路输出用于丢弃当前扫描的帧行的适当信号。 同样，如果位反转的当前列数大于水平缩放常数，则比较器电路向缩放控制器和地址发生器输出适当的信号，以将当前扫描的像素存储在帧缓冲器中。 否则，比较器电路输出适当的信号，以丢弃当前扫描的像素。

公开(公告)号：US5140544A

公开(公告)日：1992-08-18

申请号：US772498

申请日：1991-10-07

Applicant: Cheun-Song Lin ,  Bor-Chuan Kuo ,  Rong-Chung Chen

Inventor： Cheun-Song Lin ,  Bor-Chuan Kuo ,  Rong-Chung Chen

IPC: G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535

Abstract: A video display system includes a frame buffer includes five sets of one or more video random access memories. An address generator for generating address locations in the frame buffer generates ship select, row select and column select address signals. Because the frame buffer comprises five sets of video random access memories, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memeory capacity in the frame buffer.

Abstract translation: 视频显示系统包括帧缓冲器，其包括五组一个或多个视频随机存取存储器。 用于在帧缓冲器中产生地址位置的地址发生器产生船选择，行选择和列选择地址信号。 因为帧缓冲器包括五组视频随机存取存储器，所以产生地址信号需要执行五分之一的操作。 因此，地址发生器包括唯一的除以5的电路，其中除法由一系列的加法和乘法执行。 与常规系统相比，本发明的视频系统在帧缓冲器中更有效地使用存储容量。