公开(公告)号：US20120126901A1

公开(公告)日：2012-05-24

申请号：US12948896

申请日：2010-11-18

申请人： Chi Tak (Gerry) LEUNG ,  Chik Wai (David) NG ,  Hing Kit KWAN ,  Wai Kit (Victor) SO ,  Po Wah CHANG ,  Wing Cheong MAK ,  Kwok Kuen KWONG

发明人： Chi Tak (Gerry) LEUNG ,  Chik Wai (David) NG ,  Hing Kit KWAN ,  Wai Kit (Victor) SO ,  Po Wah CHANG ,  Wing Cheong MAK ,  Kwok Kuen KWONG

IPC分类号： H03L7/00

CPC分类号： H03L7/08

摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

摘要翻译： 频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。 该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。 减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。 当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。 由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。 可以通过对减法器中的反馈电阻进行编程来调整抖动度。 减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。

公开(公告)号：US08188798B1

公开(公告)日：2012-05-29

申请号：US12948896

申请日：2010-11-18

申请人： Chi Tak (Gerry) Leung ,  Chik Wai (David) Ng ,  Hing Kit Kwan ,  Wai Kit (Victor) So ,  Po Wah (Patrick) Chang ,  Wing Cheong Mak ,  Kwok Kuen (David) Kwong

发明人： Chi Tak (Gerry) Leung ,  Chik Wai (David) Ng ,  Hing Kit Kwan ,  Wai Kit (Victor) So ,  Po Wah (Patrick) Chang ,  Wing Cheong Mak ,  Kwok Kuen (David) Kwong

IPC分类号： H03B29/00 ,  H03K3/26

CPC分类号： H03L7/08

摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

摘要翻译： 频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。 该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。 减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。 当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。 由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。 可以通过对减法器中的反馈电阻进行编程来调整抖动度。 减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。